Posts Tagged ‘Intel’
Thursday, December 7th, 2017
This week on Thursday, December 14th, the second annual edition of REUSE 2017 will unfold in Silicon Valley. It’s a gathering crafted specifically for the vendors of IP blocks, and now whole sub-systems, those pieces of the puzzle which allow the vendors’ customers to design and produce electronic products more efficiently and with better results.
It goes without saying that IP is a pivotal part of the semiconductor supply chain today. Organizations like Arm and Synopsys reap huge benefits from being among the principal suppliers of that IP. But there are hundreds of IP companies in the world – big, medium, and small – that also provide IP.
Potentially, they could all be participating in something like Reuse 2017. Arm, for instance, is participating in the conference, along with dozens of smaller companies. Synopsys, however, is not.
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Tags: Achronix, Aldec, Andes Technology, Aphion, Archband, ARM, Avery Design Systems, CAST, Certus Semiconductor, ChipEstimate.com, City Semiconductor, Corigine, DAC, eFabless, FlexLogix, Intel, Intrinsic ID, IP-SoC, Menta, Mixel, Mobile Semiconductor, Mobiveil, Moortec, NSCore, NVM Engines, OmniDesign, Open-Silicon, QuickLogic, Reuse 2017, RISC-V, Samsung, Semi IP Systems, SiFive, Silicon Creations, Silvaco, Sintegra, SmartFlow, Sofics, Sonics, Surecore, True Circuits, Uniquify
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Thursday, October 5th, 2017
Hangzhou C-SKY Microsystems, a 32-bit CPU vendor, became a member of the ESD Alliance in 2016 and was described at the time as “the first IP company from China to join.”
Founded in 2001, C-Sky has “developed 7 types of embedded CPUs covering a wide range of embedded applications including smart devices in IoT, digital audio and video, information security, network and communications, industrial control and automotive electronics. It is the only embedded CPU volume provider in China with its own instruction set architecture, the Yun-on-Chip architecture developed in conjunction with Alibaba.”
C-Sky is a growing IP company serving an enormous market. I spoke recently by phone with Dr. Xiaoning Qi, CEO at C-Sky, who was in California attending meetings. No stranger to Silicon Valley, he previously served at Intel, Rambus, Synopsys, and Sun, after completing his Ph.D. under Prof. Robert Dutton at Stanford.
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Tags: Aart de Geus, Alibaba, ARM, Asia-Pacific Leadership Council, Bob Smith, C-Sky Microsystem Corp., Chenming Hu, Chi-Foon Chan, Chinese American Semiconductor Professional Association, ESD Alliance, GSA, IEEE, Intel, Mentor Graphics, Microsoft, NB-IoT, Rambus, Robert Dutton, SMIC, Stanford, Subhasish Mitra, Sun Microsystems, TSMC, Wally Rhines, Xiaoning Qi, ZTE
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Thursday, May 18th, 2017
Here begins the first of four dialogs about Grand Challenges in IP. This first installment is a conversation with Sonics co-Founder and CEO Grant Pierce, who also currently serves as Chair of the ESD Alliance. We spoke by phone earlier this week.
Asked to enumerate the Grand Challenges in IP he sees today, Pierce began: “Having been in the industry for 20 years myself, I am surprised that we still have some challenges ahead of us. We have new entrants into the industry that are more focused at the system level, however, with customers coming in to interact with the IP guys directly to get their custom designs done.
“What I am seeing today, versus 20 years ago, is the emergence of Machine Learning. And that brings with it some technical challenges. On the one hand, they are very familiar – the age-old challenges about bandwidth and throughput – but on the other hand, they are also very new. Today’s applications are driving things together in a totally new way.
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Tags: ARM, ESD Alliance, Grant Pierce, Intel, Machine Learning, Miles Davis, MIPS, NVIDIA, RISC architecture, Sonics
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Thursday, April 27th, 2017
Tom Alsop and the team at Accellera are elated: The UVM standard has been accepted by the IEEE as 1800.2 and congratulations are certainly in order.
The effort has consumed upwards of 10 years, and represents thousands of man-hours of effort, consultation, compromise, consensus building, rinse and repeat. Over and over until the final product was polished, presented and approved by the IEEE. Not an easy process by anybody’s estimation.
When we spoke by phone this week about the Accellera announcement, I asked Tom Alsop [Principal Engineer at Intel] how difficult the whole thing had actually been.
He chuckled slightly: “For us, it was fairly difficult.”
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Tags: Accellera, Accellera Systems Initiative, Cadence, IEEE 1800 SystemVerilog standard, IEEE 1800.2, IEEE Get Program, IEEE Standards Association, Intel, Joe Daniels, Jonathan Goldberg, Justin Refice, Konstantinos Karachalios, Lu Dai, NVIDIA, Stan Krolikoski, SystemVerilog, Tom Alsop, Universal Verification Methodology, UVM, UVM Working Group
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Thursday, February 16th, 2017
Millions of people are talking about when we will stop driving our cars, many thousands are working on it, and six among those thousands made an appearance Tuesday evening, February 7th, on a panel at IEEE’s International Solid State Circuits Conference in San Francisco.
Over the course of the hour, the six speakers outlined their different visions of the technical roadmap that must be pursued to achieve fully autonomous cars. Of the six speakers, however, only three actually attempted to answer the panel prompt and their answers were wildly disparate.
So when will we stop driving our cars? 1) It’s impossible to know. 2) Not until 2030. 3) We already are beginning to stop driving our cars.
The panel was moderated by a senior Intel engineer, heavily involved in the company’s newly organized business unit specifically focused on autonomous driving systems.
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Tags: Autonomous driving cars, Daimler, Denso International America, IEEE ISSCC, Infineon, Intel, Jurgen Dickmann, Markus Tremmel, NVIDIA, Patrick Leteinturier, Robert Bosch, Roger Berg, Sahin Kirtavit, Self-driving cars, Umberto Santoni
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Thursday, January 19th, 2017
At the ESD Alliance panel on the Cadence campus Wednesday night, it was Vista Ventures’ Jim Hogan who suggested the little open-source processor architecture called RISC-V will prove itself to be a plucky survivor when looming market realities hit 800-pound proprietary vendors like ARM and Intel. Hogan suggested RISC-V is positioned to survive that pending apocalypse just like “the mammals after the asteroid.”
Pretty dramatic stuff.
Hence it should not have been surprising, at the end of the 75-minute discussion on stage between Jim Hogan and Microsemi’s Ted Speers and SiFive’s Yunsup Lee, that I raised my hand and asked why Simon Segars was not in the room. After all, Simon Segars is both CEO of ARM and a key member of the Board of the Alliance that organized the Hogan-Speers-Lee program – a program where the emerging RISC-V movement was described as poised to upend the primacy of ARM etc.
Hogan responded to my question without answering: “Look, ARM is challenging by serving the low-cost processor market. License fees, royalty fees – that is what ARM wants for their low-power edge-based device. I think it was Simon, for example, who started talking to The Street about his economic strategy. It’s not really about what the best technology is, but about the economics. This is what gets the traction, and ARM will respond in an economic way.”
“Yes,” Ted Speers added, “and Intel and Imagination will also respond.”
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Tags: ARM, Dave Paterson, ESD Alliance, Imagination Technologies, Intel, Jim Hogan, John Hennessy, Linley Group, Microsemi, Olivier Bernard, Rick O'Connor, RISC-V, RISC-V Foundation, SiFive, Simon Segars, Stanford, Ted Speers, U.C. Berkeley, Vista Ventures, Yunsup Lee
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Thursday, July 21st, 2016
Who better qualified to post reactions to this week’s astonishing news out of Tokyo and Cambridge – SoftBank is buying ARM in an all-cash deal for 24.3 billion British pounds – than the leaders of two highly regarded IP companies and an articulate Brit with total street cred in EDA.
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Tags: ARM. SoftBank, Brexit, CAST IP, Dave Kelf, Hal Barbour, Intel, IoT, IPextreme, NXP/Freescale, OneSpin, RISC-V project, TI, Warren Savage
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Wednesday, January 27th, 2016
The book that Sir Robin Saxby has been waiting for has finally been written: “Mobile Unleashed: The Origin and Evolution of ARM Processors in Our Devices”.
Authored by SemiWiki’s Dan Nenni and Don Dingee, the book “delivers an informative look at events and technology that powered the mobile device industry to worldwide adoption.”
When I spoke with Dingee by phone this week, he said the book represents an enormous amount of work: “Sixteen months of intense research, 270 pages and over 800 footnotes.”
Other books have been written about ARM, he acknowledged, but this one is different: “People ask if this is a technology book or the story of ARM and I say, in truth it’s a little bit of both.”
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Tags: ARM, Dan Nenni, Don Dingee, Google, Huawei, Intel, MediaTek, Mentor Graphics, Microsoft, MIPS, Motorola, Nokia, Qualcomm, Sir Robin Saxby, TI, Wally Rhines
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Wednesday, August 19th, 2015
When it comes to Docea Power, there’s no scoop. There’s no news at all. Except of course that they’ve been bought by Intel, which in itself is pretty big news for any company. Except apparently Docea. There was/is no press release and was/is no access to details on the deal. Nothing.
There is proof, however, that the acquisition took place. Right on the front of the Docea website. But that’s it.
Having interviewed the brothers who founded Docea, Ghislain and Sylvain Kaiser, multiple times over the years – at DATE in Europe and at various conferences here in the U.S. — I certainly hoped to know more, and I tried. But their people — the ones who reached out to journalists in June asking for meetings with the company at DAC, back when Docea still existed — were candid: “There is no press release available. And there will be no talk with Docea founders”
And that’s it. Except for this …
Lucky Intel!
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Tags: ACEplorer 2.0, AceThermalModeler, ANSYS, DOCEA Power, Ghislain Kaiser, Infineon, Intel, Mentor, ST-Ericsson, STMicro, Sylvain Kaiser
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Thursday, October 2nd, 2014
This blog requires a long, tall cup of coffee: Go get one, put your feet up, and plow on through. ARM TechCon 2014 took place this week at the Santa Clara Convention Center, and as an indication of what the industry feels is important right now, the following is a complex snapshot of press releases issued by various TechCon exhibitors highlighting their progress in the days leading up to and including the show. Listed first are the three main ARM press releases, then the other exhibitors are showcased.
By the way, the answer to what the industry thinks is important today? If the following is any indication, it’s IoT all the way down, with a dollop of FinFET and low-power thrown in for good measure. And if you don’t know IoT means Internet of Things, you haven’t been listening – particularly as Freescale says in their Press Release: “Analyst research firm Gartner estimates that the IoT will include 26 billion units installed by 2020, and by that time, IoT product and service suppliers will generate incremental revenue exceeding $300 billion, mostly in services.”
Another possible conclusion from the following: If you’re still holding out hope the Design Automation Conference is anchor tenant of the conference year, you should let that go. The amount of news these companies are releasing around ARM TechCon far out weighs what they’re releasing around DAC.
** ARM announced on October 1st “two new physical IP implementation solutions for its silicon partners to help simplify the path to implementation for their FinFET physical designs. ARM Artisan Power Grid Architect will reduce overall design time by creating optimal SoC power grid layouts, while ARM Artisan Signoff Architect increases accuracy and precision in managing on-chip variation over existing methodologies. These new physical IP implementation solutions strengthen the commitment from ARM to enable delivery of real silicon with the speed consumers are demanding.”
** ARM announced on October 1st, mbed OS, a free operating system for ARM Cortex-M processor based devices that consolidates the fundamental building blocks of the IoT in one integrated set of software components; mbed Device Server, a licensable software product that provides the required server-side technologies to connect and manage devices in a secure way, that also provides a bridge between the protocols designed for use on IoT devices and the APIs that are used by web developers; and mbed.org, the focus point for a community of more than 70,000 developers around mbed. The website provides a comprehensive database of hardware development kits, a repository for reusable software components, reference applications, documentation and web-based development tools.
** ARM and TSMC announced on October 2nd a new multi-year agreement that will deliver up ARMv8-A processor IP optimized for TSMC 10FinFET process technology. Per the Press Release: “Because of the success in scaling from 20SoC to 16FinFET, ARM and TSMC have decided to collaborate again for 10FinFET. This early path-finding work will provide valuable learning to enable physical design IP and methodologies in support of customers to tape-out 10FinFET designs as early as Q4 2015.”
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Tags: Acacia Communications, Airbus Defence and Space, Aldec, Altium Ltd., AMD, ANSYS, AppliedMicro, ARicent, ARM, ARM TechCon 2014, Arteris, ASSET InterTech, Atmel, Avago Technologies, Aviva Energy Corp., Cadence, Carbon Design Systems, Cavium, Cisco, Codasip, Doulos, Esterel, Express Logic, FreeBSD Foundation, Freescale, Gartner, GlobalFoundries, Green Hills Software, HP, IAR Systems, Intel, Internet of Things, IPSO Alliance, Lauterbach, LogMeIn, Mentor Graphics, Micrium, MontaVista Software, Mouser Electronics, Open-Silicon, P&E Microcomputer Systems, Rambus, Real Intent, Renesas Electronics, S2C, Samsung Electronics, SatixFy Ltd., SeeControl, SEGGER, Si2, SOMNIUM Technologies, Sonics, Spansion, STMicro, SYSGO, Teledyne LeCroy, TI, Toradex, TSMC, Undo Software, Uniquify, VanGogh Imaging, Vector Software, Wind River, Xilinx, XMOS, Zebra Technologies, Zuse Institute Berlin
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