Posts Tagged ‘Xilinx’
Wednesday, October 11th, 2017
After two years in Austin, the Design Automation Conference is returning to San Francisco for two good reasons: The City’s Moscone Convention Center has been thoroughly remodeled since DAC’s last visit in 2015 – enlarged, reworked, modernized – and the industries that fuel DAC – electronic design automation, system design, IP, and embedded systems – have a powerful and historic presence in Silicon Valley, a where place many in these disciplines work and live.
Hence June 2018 will witness a glamorous return to the Bay Area for DAC, and all its stakeholders, not the least being next year’s General Chair and Notre Dame CSE Professor, Dr. X. Sharon Hu.
In a recent phone call, Hu said it’s particularly exciting to be coming back to San Francisco, because the City is one of her favorite venues.
In preparation for DAC in 2018 and to similarly enhance anticipation for her Executive Committee – that group of hard-working volunteers who work the magic each year bringing DAC to fruition – Hu recently hosted a team building exercise here in 2017 in the just-reopened Moscone West portion of the massive complex. The group made sushi, and with pictures of the cook-off trending on Twitter, she laughed when I asked how it all went.
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Tags: ACM SIGDA, DAC 2018, DAC Under 40 Innovators, Design Automation Conference, DJI, Dr. X. Sharon Hu, Dr. Xin Li, Duke University, Hall-Erickson, IEEE, Michelle Clancy, Notre Dame, NVIDIA, Patrick Groeneveld, Richard Newton Young Student Fellows, Xilinx
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Thursday, October 2nd, 2014
This blog requires a long, tall cup of coffee: Go get one, put your feet up, and plow on through. ARM TechCon 2014 took place this week at the Santa Clara Convention Center, and as an indication of what the industry feels is important right now, the following is a complex snapshot of press releases issued by various TechCon exhibitors highlighting their progress in the days leading up to and including the show. Listed first are the three main ARM press releases, then the other exhibitors are showcased.
By the way, the answer to what the industry thinks is important today? If the following is any indication, it’s IoT all the way down, with a dollop of FinFET and low-power thrown in for good measure. And if you don’t know IoT means Internet of Things, you haven’t been listening – particularly as Freescale says in their Press Release: “Analyst research firm Gartner estimates that the IoT will include 26 billion units installed by 2020, and by that time, IoT product and service suppliers will generate incremental revenue exceeding $300 billion, mostly in services.”
Another possible conclusion from the following: If you’re still holding out hope the Design Automation Conference is anchor tenant of the conference year, you should let that go. The amount of news these companies are releasing around ARM TechCon far out weighs what they’re releasing around DAC.
** ARM announced on October 1st “two new physical IP implementation solutions for its silicon partners to help simplify the path to implementation for their FinFET physical designs. ARM Artisan Power Grid Architect will reduce overall design time by creating optimal SoC power grid layouts, while ARM Artisan Signoff Architect increases accuracy and precision in managing on-chip variation over existing methodologies. These new physical IP implementation solutions strengthen the commitment from ARM to enable delivery of real silicon with the speed consumers are demanding.”
** ARM announced on October 1st, mbed OS, a free operating system for ARM Cortex-M processor based devices that consolidates the fundamental building blocks of the IoT in one integrated set of software components; mbed Device Server, a licensable software product that provides the required server-side technologies to connect and manage devices in a secure way, that also provides a bridge between the protocols designed for use on IoT devices and the APIs that are used by web developers; and mbed.org, the focus point for a community of more than 70,000 developers around mbed. The website provides a comprehensive database of hardware development kits, a repository for reusable software components, reference applications, documentation and web-based development tools.
** ARM and TSMC announced on October 2nd a new multi-year agreement that will deliver up ARMv8-A processor IP optimized for TSMC 10FinFET process technology. Per the Press Release: “Because of the success in scaling from 20SoC to 16FinFET, ARM and TSMC have decided to collaborate again for 10FinFET. This early path-finding work will provide valuable learning to enable physical design IP and methodologies in support of customers to tape-out 10FinFET designs as early as Q4 2015.”
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Tags: Acacia Communications, Airbus Defence and Space, Aldec, Altium Ltd., AMD, ANSYS, AppliedMicro, ARicent, ARM, ARM TechCon 2014, Arteris, ASSET InterTech, Atmel, Avago Technologies, Aviva Energy Corp., Cadence, Carbon Design Systems, Cavium, Cisco, Codasip, Doulos, Esterel, Express Logic, FreeBSD Foundation, Freescale, Gartner, GlobalFoundries, Green Hills Software, HP, IAR Systems, Intel, Internet of Things, IPSO Alliance, Lauterbach, LogMeIn, Mentor Graphics, Micrium, MontaVista Software, Mouser Electronics, Open-Silicon, P&E Microcomputer Systems, Rambus, Real Intent, Renesas Electronics, S2C, Samsung Electronics, SatixFy Ltd., SeeControl, SEGGER, Si2, SOMNIUM Technologies, Sonics, Spansion, STMicro, Synopsys, SYSGO, Teledyne LeCroy, TI, Toradex, TSMC, Undo Software, Uniquify, VanGogh Imaging, Vector Software, Wind River, Xilinx, XMOS, Zebra Technologies, Zuse Institute Berlin
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Monday, July 28th, 2014
There are three kinds of written word in the world today: books, newspapers/magazines, and all of the rest of it which now lives on the shifting sands of an ever-evolving electronic substrate. Even today, however, even as those ‘effervescent electrons’ garner more and more readers, it’s books-on-paper that continue to hold the most caché, the most gravitas-laden sense of permanence, and the most awe-inspring-for-the-ages kind of wow factor: Really? You wrote a book? Wow!
Hence, when a 220-page book-on-paper called Fabless: The Transformation of the Semiconductor Industry was made available to the EDA community at the 51st annual Design Automation Conference this past month in San Francisco, it was worth noting for several reasons: For the gravitas of the offering; For the permanence of the tome; And for the price, which thanks to eSilicon Corp. was free to all for the taking.
Written by SemiWiki.com gurus Daniel Nenni and Paul McLellan, this Fabulous Fabless book-on-paper was handed out during a buzzy networking event on the spacious East Side of Moscone Center early one evening during the week of DAC in June. At that noisy, ebullient reception, the libations were flowing liberally and so was the printed word.
Anyone milling about in the crowd quickly became the proud owner of Nenni/McLellan’s cheery, well-written history of the world – that special world consisting of everything termed “technology” since 1947 – and could even get signed copies, if they were able to elbow their way across the room to where the authors were perched side-by-side at a table with the express purpose of applying ink-to-paper on the front piece of their book.
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Tags: Altera, AMD, Apple, ARM, Arteris, Atrenta, C&T, Cadence, Calypto, CEVA, Chartered, Cliosoft, Coventer, Daniel Nenni, Docea, eSilicon, Fabless Semiconductor, GlobalFoundries, GSA, Imagination Technologies, Intel, Jasper, Mentor, Paul McLellan, SemiWiki.com, Sidense, Silvaco, Solido, Sonics, Synopsys, Tanner, TSMC, UMC, VLSI Technology, Xilinx
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Thursday, October 17th, 2013
A brief sampler of recent announcements on the IP front reveal distinct themes in the marketplace. IP development and integration require a viable ecosystem of suppliers and tool vendors; automotive, audio and mobile apps continue to be important targets for IP developers whose customers seek better safety, longer battery life, and truer sound (particularly for sporting events and concerts of aging rockers); IP interfaces remain crucial; and platform-based design totally depends on further enhancements in IP technologies.
Additionally, acquisitions definitely pan out for the companies smart enough to snap up the good ones: Synopsys/ARC, Cadence/Tensilica, and Imagination/MIPS.
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Tags: Altera, ARC, ARM, ASSET InterTech, Cadence, CAST, Dolby, Freescale Semiconductor, Geir Skaaden, Geoff Lees, Imagination Technologies, IPextreme, Jack Guedj, John Couling, John Koeter, Martin Lund, Mentor Graphics, MIPS, Nikos Zervas, Pete Hutton, Suk Lee, Synopsys, Tensilica, Tom Halfhill, Tony King-Smith, TSMC, Warren Savage, Xilinx
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Thursday, February 14th, 2013
After the euphoniously monikered IP provider, Uniquify, announced several weeks ago that the more whimsically monikered organization, Pixelworks, is using Uniquify’s DDR memory controller subsystem IP for multiple distinct processors that Pixelworks is, in turn, providing to TV makers who make 4Kx2K ultra high-def systems, one question still remained: How did Pixelworks know to use Uniquify’s offering?
According to a January 2013 article in IEEE Spectrum, knowing what IP to use in a project here in the 21st century is fairly easy knowledge to come by. I don’t know what planet the author of the op-ed piece, “Other People’s Knowledge”, lives on but it doesn’t seem to be the one that I hear about from the folks who make or buy third-party IP.
In fact, those people seem to indicate that knowing what IP to use in a particular project continues to be far more art than science. In particular, because until a system, or sub-system, is fully defined, modeled and simulated – let alone, manufactured and deployed in the field – one can never really know how a piece of IP is going to work in the environment into which it’s been placed.
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Tags: BarcoSilix, Cadence, DDR memory controller IP, Eureka Technology, IP, Synopsys, TI, Uniquify, Xilinx
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Thursday, December 13th, 2012
France-based Reflex CES [Custom Embedded Systems] announced this week what the company calls “the industry’s first release of the Reflex CES Aurora-like IP core based on Altera FPGAs. The core enables interoperability between Xilinx Virtex-6 LXT and Altera Stratix IV and Stratix V GX FPGAs.”
Sylvain Neveu, Reflex CES Co-founder and CEO, is quoted: “With our Reflex CES Aurora-like IP core, designers can easily migrate to new FPGA families with minimum risks, reuse their previous designs, and choose the best FPGA technology for their boards and systems using the Aurora protocol.”
So if that’s an Aurora-like IP core, what’s an Aurora IP core? The answer is, it’s from Xilinx:
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Tags: Altera, Aurora IP core, Aurora-like IP core, IEDM, Reflex CES, Sylvain Neveu, Xilinx
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