Posts Tagged ‘Mentor Graphics’
Thursday, December 21st, 2017
San Francisco-based Methodics has been addressing both the enterprise data management and IP reuse/lifecycle management markets for over 10 years.
The company’s strategy of integrating their lifecycle management tools with products like Perforce version control software and Subversion from Apache, means they dovetail with industry standard solutions. As a natural outgrowth from that, Methodics’ IP-related offerings also work at the enterprise level, helping the customer’s distributed team coordinate and catalog IP use, and keeping track of third-party IP use as well.
In my recent phone call with Methodics CEO Simon Butler, it was clear the company is seeing the fruits of their many years of hard labor come to fruition.
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Tags: Apache, Cadence, DAC, ESD Alliance, Mentor Graphics, Methodics, Perforce, Simon Butler
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Thursday, October 5th, 2017
Hangzhou C-SKY Microsystems, a 32-bit CPU vendor, became a member of the ESD Alliance in 2016 and was described at the time as “the first IP company from China to join.”
Founded in 2001, C-Sky has “developed 7 types of embedded CPUs covering a wide range of embedded applications including smart devices in IoT, digital audio and video, information security, network and communications, industrial control and automotive electronics. It is the only embedded CPU volume provider in China with its own instruction set architecture, the Yun-on-Chip architecture developed in conjunction with Alibaba.”
C-Sky is a growing IP company serving an enormous market. I spoke recently by phone with Dr. Xiaoning Qi, CEO at C-Sky, who was in California attending meetings. No stranger to Silicon Valley, he previously served at Intel, Rambus, Synopsys, and Sun, after completing his Ph.D. under Prof. Robert Dutton at Stanford.
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Tags: Aart de Geus, Alibaba, ARM, Asia-Pacific Leadership Council, Bob Smith, C-Sky Microsystem Corp., Chenming Hu, Chi-Foon Chan, Chinese American Semiconductor Professional Association, ESD Alliance, GSA, IEEE, Intel, Mentor Graphics, Microsoft, NB-IoT, Rambus, Robert Dutton, SMIC, Stanford, Subhasish Mitra, Sun Microsystems, Synopsys, TSMC, Wally Rhines, Xiaoning Qi, ZTE
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Thursday, September 28th, 2017
Sage Design Automation offers iDRM – integrated design rule management – a “true design rule compiler that enables quick graphical capturing of design rules and uses them as executable expressions for Specification, Communication, Validation, DRC, Analysis, Deck validation and coverage, and DRC deck generation.”
But this is not about Sage, it’s about how Sage fits into an evolving industry from the point of view of Raul Camposano, EDA veteran, former CTO at Synopsys, and currently CEO at Sage. Like so many serving in leadership roles in the industry, Dr. Camposano is a man of good cheer and an optimistic observer.
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Tags: Dan Nenni, DRC decks, ESD Alliance, Giovanni De Micheli, IoT, Kurt Keutzer, Mead Conway, Mentor Graphics, Moore's Law, Raul Camposano, Sage, Silicon Catalyst, Synopsys, TSMC
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Thursday, August 3rd, 2017
As national and international news crashes over the shore, wave after wave, it’s easy to lose track of any particular item amidst the churning foam. The story discussed here, however, floats more visibly atop the flotsam and jetsam because it’s relevant to the IP and EDA industries.
Several weeks ago, Siemens AG – a German company – was caught-up in a violation of a part of the current EU sanctions against Russia. Siemens’s power turbines, having been sold to Russia – which was not a violation – were then allegedly modified and shipped off to Crimea for installation there – which was a violation.
You remember Crimea. It was part of Ukraine until 2014, and then it was not.
Anyway when the turbine situation was uncovered, the EU was not happy with Siemens; Siemens was not happy with Russia; if Russia or Crimea were unhappy with anyone, they kept it to themselves.
As a result of these revelations, Siemens AG now faces a fine from the EU, and has canceled several high-profile, lucrative business deals with Russian firms. Siemens is mad – slightly less rich, and mad.
Which brings us to Mentor Graphics. Such experts we are, who have had the chance to learn about Export Controls from the likes of Cadence’s Larry Disenhof or SmartFlow’s Ted Miracco, and it’s that knowledge which seems relevant to Mentor.
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Tags: Crimea, EU sanctions, Larry Disenhof, Mentor Graphics, Russia, Siemens AG, Siemens USA, Ted Miracco
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Wednesday, July 26th, 2017
It’s good to know another EDA startup has emerged, they’ve been in such short supply of late.
Austin-based Austemper Design Systems is an EDA startup focused on functional safety that had the good luck to find the Design Automation Conference in their own front yard this year – making it easy for the company to exhibit in Austin and showcase their newly announced suite of tools.
Speaking by phone in a recent call, Austemper Founder & CEO Sanjay Pillay said, “We offer four different tools in our suite, one that analyzes quantitative metrics, two for design automation that go in and add diagnostic conversions and can be used for a single block of IP or for the entire design, and a fourth tool that runs fault-injection analysis.”
Given that the company has only been underway since March 2015, I suggested that tool portfolio represents a lot of productivity over a short amount of time.
Pillay agreed: “Although we are young, we are already working with the largest semiconductor companies in the world, and in the process of negotiating licenses with others.
“DAC was a great place to announce our products. We had more than 30 meetings and demonstrations with potential customers and partners during DAC. It was also an opportunity for us to meet in person with people we have interacted with over e-mails and conference calls, to make that human connection.”
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Tags: ADAS, Advanced Driver Assistance Systems, Austemper Design Systems, Cirrus Logic, DAC 2017, HGST/STEC, ISO 26262, Maxim, Mentor Graphics, Sanjay Pillay, Synopsys. Cadence
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Thursday, May 25th, 2017
This conversation with Hal Barbour, Chairman at CAST IP, is the second of four dialogs about Grand Challenges in IP.
The first installment in the series, published last week, was a conversation with Sonics co-Founder and CEO Grant Pierce.
Pierce argues that today’s Grand Challenges in IP center around the complexities of delivering sub-systems and related technical expertise to customers, helping develop edge-node devices targeted at Machine Learning, and providing IP for myriad automotive systems – all while meeting demands for greater bandwidth and throughput, and astonishingly low power.
In this week’s installment in the series, Hal Barbour talks about a completely different set of Grand Challenges in IP – those related to the business issues surrounding the industry.
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Tags: ARM, Beyond Semiconductor, Cadence, CAST IP, Fraunhofer Institute, Hal Barbour, Mentor Graphics, Nikos Zervas, Ocean Logic, Paul Lindemann, Sandgate, Silesia Devices, SoC Solutions, SoftBank, Synopsys, View Logic
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Thursday, April 13th, 2017
Something eerie and inexplicable happened on Thursday evening, April 6th. Out of nowhere, an intense storm swept through the Bay Area, unannounced and without warning. The skies darkened, the winds howled, severe rain pelted the crowded, suddenly dangerous freeways, and hundreds of thousands lost power.
Meanwhile, exactly in the midst of the most violent part of this mysterious storm, the CEOs of the four most important companies within the ESD Alliance sat on stools in front of an audience assembled at Synopsys and chatted about this, that, and the other. Seemingly oblivious to the profound violence unleashing itself just outside the windows, they acted as if nothing was amiss.
Everything in the industry – and the world – was in order: Wonderful, with the data pointing continuously up and to the right, and everywhere ample evidence for a bullish, optimistic, and excited outlook on the future of EDA and IP.
No matter that Nature was having its way out there in the darkness, that the U.S. had bombed Syria the hour before their discussion began, that the drumbeat for answers about entanglements with Russia was quickening, or difficult conversations with the President of the PRC were underway that very day in Florida – the CEOs of Synopsys, Cadence, Siemens/Mentor Graphics and SoftBank/ARM sat relaxed and easy, basking in the evident vitality of the EDA and IP industries, and allowing themselves to be shepherded through a congenial confab of confident chit-chat by Ed Sperling of Semiconductor Engineering fame.
That fact that the vagaries of Nature never came into the conversation was not surprising; the fact the Mr. Sperling refused all opportunities to bring what he termed as “politics” into the conversation was quite the opposite. Surprising, that is.
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Tags: Aart de Geus, ARM, Brexit, Cadence, Ed Sperling, ESD Alliance, H1-B visas, Lip-Bu Tan, Mentor Graphics, Semiconductor Engineering, Siemens, Simon Segars, SoftBank, Synopsys, Walden C. Rhines
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Thursday, February 23rd, 2017
Oski Technology has added a new page to its playbook. Now it’s not just a services company, it’s an IP company as well. This week, the company announced it’s Formal Verification IP Library targeted at those companies using ARM’s AMBA interface protocols.
When we spoke on the phone about the announcement, I asked Oski VP of Applications Engineering Roger Sabbagh why now for this product release. He said: “I personally have been working in Formal since the year 2000, back when I joined 0-In, and over the years I’ve learned that formal adoption grows slowly.
“Yet although there has never been a knee in the curve, we have seen some important developments in the industry. Synopsys developed PC Formal and Cadence bought Jasper, both indicating that Formal is catching on slowly but surely.”
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Tags: 0-In Design, Cadence, DVCon 2017, Formal sign-off, Jasper Design Automation, Mentor Graphics, Oski Tehnology, Roger Sabbagh, Synopsys
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Thursday, February 9th, 2017
This week, the ESD Alliance announced that Sonics CEO Grant Pierce has been elected chair of the organization’s Board of Directors. His election is unique in several ways: Pierce is the first CEO of an IP company to lead the Alliance; he replaces two co-chairs, Cadence CEO Lip-Bu Tan and PDF Solutions, John Kibarian; and he is only the second CEO of a non-publicly traded company to serve as Board Chair, the other being Jasper CEO Kathryn Kranen who took the reins in 2012.
When Pierce and I spoke by phone on Tuesday about his election, he noted the unique circumstances of his new leadership role: “When I joined the board several years ago, it was with the intention to add a new point of view to what was then the EDA Consortium, to help the organization reflect the emerging reality of what was happening in the marketplace with respect to IP companies.
“In some ways, the IP companies consider themselves to be a necessary evil. Every chip developed today involves some sort of third-party IP, so having a place on the Board of the ESD Alliance is essential.”
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Tags: Aart de Geus, Amit Gupta, ARM, Bob Smith, Cadence, Cadence Design Systems, Dean Drako, EDA Consortium, EDAC, ESD Alliance, ESDA, IC Manage, John Kibarian, Lanza techVentures, Lip-Bu Tan, Lucio Lanza, Mentor Graphics, PDF Solutions, Simon Segars, Solido Design Automation, Sonics, Synopsys, Wally Rhines
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Thursday, October 27th, 2016
Raise your hand if you think innovation comes out of small, nimble, edgy startups. Keep your hand up if you think consolidation is antithetical to the inventive culture closely associated with small, nimble edgy startups where everybody works outside of their job description and above their grade. Now put your hand down and tell us what you think about yet another merger in the semiconductor industry.
Yes, happy for investors that Qualcomm is buying NXP, but the end result will be a nasty one for technical innovators in EDA. Yet another reduction in the number of customers for EDA tools. Not necessarily a reduction in the number of seats, but a reduction in the number of actual separate corporate entities looking for tools for chip design.
Of course, for those who love large, lumbering organizations with almost as many people in the typing pool as in the engineering pool – more consolidation is great news for the semiconductor business and for the electronic design automation business, as well.
However, for those who still remember when EDA was a Wild West full of crazy startups, wacky business ideas, and loads of shifting sands between a constantly morphing/re-morphing population of EDA startups and an also-always morphing/re-morphing population of chip-design customers – take note: Those days are gone. Forever.
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Tags: ARM, Cadence, Mentor Graphics, NXP, Qualcomm, Synopsys
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