Jacek Hanke is the CEO in Digital Core Design. He established DCD with his colleagues in 1999 - they all studied at The Silesian University of Technology, Gliwice, Poland. When he graduated in 1999, he got some interesting job posts from big companies from USA, Japan and Western Europe. But he … More »
What the FAQ with obsolete & EOL parts?
February 11th, 2020 by Jacek Hanke
There’s an old saying that we like the things we know. The same goes with CPUs and other electronics. We use some specific ASICs or FPGAs for years, cause they just are there. And what to do if they become obsolete and manufacturer decided not to offer them anymore?
DCD’s got an answer. Use 1:1 replacement for EOL, which is 100% compatible with an original chip. Both FPGAs and ASICs offer great variety of solutions which can be efficiently and effortlessly utilized in the final design. Here’s a FAQ to help you move forward.
Jacek Hanke, DCD’s CEO says that the experience his company gained during last 20 years is priceless. – Among 70 different architectures one can easily find obsolete and hard to find discontinued electronic components – he says. Basing on hitherto experience, we can say that:
Which CPUs can be replaced?
Every – says Jacek Hanke – among them IP cores equivalent to obsolete chips that cover the following processors:
Which companies replaced EOL product and which products?
Among customers who trusted DCD and ordered solutions for obsolete parts one can find e.g. Caterpillar, Siemens, Bombardier, Sagem and dozens of other (NDA). Our R&D designed for these companies e.g. pin to pin compatible Motorola’s HC11.
HC11? Sounds interesting?
One of our customers from sunny California sent us an e-mail: “We received our first silicon with DCD’s soft core “DF6811”. We manufactured our silicon in TSMC’s 0.18 um, LP process. The results have been excellent with no functional or timing failure.”
And what about gate utilization in ASIC and FPGA?
DF6811 design includes: CPU, PORTS, SCI, SPI, COM/CAP, TIMER, WATCHDOG, RTI. Its target library is TSMC 0.25u process. Synthesis results look as follows: when area optimized – 12000 gates 100 MHz and when speed optimized 15700 gates 220 MHz. Power consumption with FULL speed at 100 MHz 25 mW (milli-Watts) 0.25 mW/MHz. Static leakage power is equal to 0.411 uW for the total DF6811 design.
1:1 chip replacement is all that you can do or can I get something more from EOL chip replacement?
DF6811 is actually the most powerful 6811 IP Core in the whole IP market. It has more than 4xfaster architecture over standard 6811, when most other cores have architecture speed rate 1x. So at same clock frequency aforementioned DF6811 Core is 4 times faster and it allows user to reduce the power consumption by using 4 times slower clock or increase the performance by setting the clock at the same level. The same you’ll get in your design 10 times faster multiplication, 16 times faster division, Program Memory, DATA Memory and external SFR’s wait state feature, support for 16MB of Data memory, support for SYNCHRONOUS program (CODE inside synchronous ROM) and DATA memories, two power saving modes: STOP and WAIT, interface for external SFR registers, fully configurable CPU features and… DoCD – DCD’s on-Chip Debugger
What about MC6802?
The D6802 is a part of mature DCD IP family of 6811, 6802, 6803 microprocessors, microcontrollers introduced in 2004. The major part of all processors from that family are common for all IP’s. Between particular cores there are only small differences. Among companies which successfully implemented IP from this family one can find e.g.: General Electric, Bombardier, Caterpilar, Harris, Siemens. Some of them are using MC6802 in safety applications – like e.g. Bombardier is using it in their railway system since 2009. As an example we can also mention an aircraft company, which search D6802 as a replacement for their safety application. The Core itself has been thoroughly evaluated, tested and most of all – technically approved. Along with an IP we provide the Test bench with set of tests and simulation script, so in tool like ModelSim you need just run single script and selected or all tests will be executed one by one, generation reports whether test passed as expected or if there is any differences between real simulation data and reference response read form file.
OK, let’s leave HC11 for a moment. What about other Motorola’s CPUs like MC68020 or M68k?
EOL M68020 chip
68020 you can implement e.g. in an FPGA (Flash or SRAM). DCD’s D68000 is upward compatible to MC68020 but it is not a replacement for 68020. The binary code compiled for 68000 will run on 68020 but binary code compiled for 68020 will not run on 68000. What we offered our customer and what he agreed and implement in his project, was an upgrade of the IP from 68000 to 68020. The development took us 9 months. Final solution has been based on D68000+BDM, which was used as a start point to design D68020.
Sounds reasonable. And what about original Motorola’s 68000?
One of the customers intended to have a compatible IP 68000 processor, compatible instruction and instruction time. Target was a Netlist version dedicated to an FPGA from Microsemi (Microchip) IGLOO2 or PolarFire. It’s worth to mention that the aforementioned netlist should be feasible to be included in VHDL project. In the first step customer wanted to verify the perfect compatibility of DCD-SEMI’s IP by usind an adapter card to replace an original card, the component 68000 Motorola by a FPGA IGLOO2 with DCD’s IP.
How was it working ?
We advise our customer that the D68000 is NOT 100% cycle compatible to MC68000. It is about 20% faster than MC68k! D68000 soft core is binary-compatible with the industry standard 68000 32-bit microcontroller. It has a 16-bit data bus and 24-bit address data bus. It is code-compatible with the MC68008 and is upward code compatible with the MC68010 virtual extensions and the MC68020 32-bit implementation of the architecture. D68000 has improved instructions set which allows execution of a program with higher performance than standard 68000 core. Adjustment to the customer specification took us 8 weeks. His goal wasn’t modification or debugging of the existing software because he had not got the source code. The first step was to check that DCD’s D68000 IP is completely transparent, that’s why customer put a 68000 emulation board, which was an FPGA that integrated DCD’s IP instead of the original MC68000 component (that board was pin to pin compatible with MC68000 component). Second step was another FPGA that integrated all the current CPU board with the IP68000. The bus cycles were identical, which was mandatory for the customer. The only difference between DCD’s and the obsolete original was that our instructions are faster, which remains a huge advantage. Below one can find the size of the D68000 in Logic Elements of IGLOO2 ( 1LE = 4lut +DFF). Here’s a table for it:
Resource Usage Libero Software Release v11.8
Do I understand right, you hardware debugger is available for M68k?
To complement the D68000, has been developed with DoCD-BDM hardware debugger, which provides debugging capability not only for the IP Core, but for the whole SoC system. The debugger is 100% compatible with BDM debug interfaces, working smoothly with its interfaces/cables: Public Domain cable, Macraigor Wiggler and P&E BDM cable. DoCD’s also fully supported by standard debugging tools like GNU GD8 debugger, Cosmic ZAP debugger and Tasking debugger. mentioned examples of proprietary IP Cores for EOL / obsolete parts replacement don’t include all the cases DCD’s been working on. Starting from 1999 till 2020 Polish company engineers mastered hundreds of designs, which replaced discontinued chips. Millions of them have been used 24/7, every day, every year – until now. If you’re wondering if the chip you need can be replaced by DCD IP Core, just give us a call, send us an e-mail at firstname.lastname@example.org or leave a message on our website www.dcd.pl
Category: IP Core Market