Posts Tagged ‘Warren Savage’
Thursday, June 1st, 2017
This is the third in a four-part series showcasing Grand Challenges in IP. The first two conversations were with Sonics CEO Grant Pierce, and CAST Board Chair Hal Barbour.
This week’s dialog is with Warren Savage, founder and CEO of IPextreme. The company was purchased by Silvaco in 2016, where Savage now serves as GM of the IP division.
Warren Savage has been an energetic leader in the IP community, working to get companies in the industry to link arms, address common concerns, and give greater visibility to the importance of their products in the global semiconductor supply chain.
When we spoke on May 24th, Savage began by addressing my question about protection for IP blocks as they move down the manufacturing chain
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Tags: CAST IP, Grant Pierce, Hal Barbour, IPextreme, Moore's Law, Silvaco, Sonics, Warren Savage
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Thursday, April 20th, 2017
There’s two kinds of conversations when it comes to electrical systems and cars. One is about the power train and the other one is about the advanced driver-assistance system, ADAS. Distinct as they may be, both of these systems can benefit from the optimizations associated with design automation, and both of these systems today are mashed up against the complexities of using third-party IP.
Chips in cars today need to manage the power train, or they need to provide safety and security for the driver – but either way, they need to work perfectly every time, all the time, and in some pretty hellish conditions. It’s hot under the hood and the road today is unforgiving. So are the lawyers.
So what’s a third-party IP provider supposed to do? Turn tail and run? Never sell into the automotive market where litigation looms larger than a sandstorm in April on the Texas Panhandle? Or try to man-up and work with the automotive market to provide IP that fits well into the chips that such customers need?
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Tags: 2017 Design Automation Conferencen, Anis Jarrar, ARM, Neil Stroud, NetSpeed Systems, NXP, Rajesh Ramanujam, Texas, Warren Savage
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Thursday, November 10th, 2016
Next Tuesday, November 15th, is the deadline for submitting research abstracts for the IP track at DAC 2017 in Austin in June. Paper manuscripts are due the following Tuesday. IP-themed session proposals are also due on that Tuesday, November 22nd, while Designer & IP Track proposals are due December 14th.
[NOTE: The December 14th date listed above is for invited Design Track & IP Track proposals. All other proposals for DAC 2017 Design Track & IP Track content can be submitted for review up until January 14, 2017. Thank you to DAC Press Chair Michelle Clancy for this important clarification.]
In other words, if you want to present within the IP Track at the 54th Design Automation Conference, you need to get going now.
The committee that will be overseeing review of these proposals is being headed up by Lattice Semiconductor’s Claude Moughanni – his group taking seriously their role in assembling an IP program that’s both informative and cutting edge.
Moughanni’s committee members include IPnest’s Eric Esteve, Synopsys’ Marc Greenberg, ARM’s Simon Rance, Freescale’s Henning Spruth, Mentor’s Farzad Zarrinfar, Intel’s Ty Garibay, Samsung’s Kelvin Low, Silvaco’s Warren Savage, and Cadence’s Karamveer Yadav – an impressive group who are indeed subject experts.
So, why should you go to all the effort to submit something for review by this group? Is there really any benefit in taking the time to participate at DAC, next year or ever?
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Tags: 54DAC, AdaptIP, ARM, ARM TechCon, Cadence, CDNLive, Claude Moughanni, Design Automation Conference, Eric Esteve, Farzad Zarrinfar, Henning Spruth, Karamveer Yadav, Kelvin Low, Mac McNamara, Marc Greenberg, Mentor, Simon Rance, SNUG, Synopsys, Ty Garibay, Warren Savage
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Thursday, November 3rd, 2016
Check out the link to know that the upcoming conference, REUSE 2016, will be something to behold. Slated for Thursday, December 1st, at the Computer History Museum, the event website is glamorous and the promise of the show profound:
“REUSE 2016 is the first of an annual conference and trade show to bring together the semiconductor IP supply chain and its customers for a full day of everything to do with semiconductor IP. Hosted in the heart of Silicon Valley at the world-famous Computer History Museum, there could not be a more appropriate venue for a day focused on the hottest segment of the semiconductor industry.”
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Tags: Abhijit Abhyankar, Bernd Stamme, Brian Gardner, Computer History Museum, Eric Stein, Hans Bouwmeester, Jim Bruister, Jim Feldhan, Meredith Lucky, REUSE 2016, Rob Ballow, Stephen Fairbanks, Tony Kozaczuk, Warren Savage
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Thursday, September 15th, 2016
Synopsys has a problem. Per Norm Kelly, speaking at the ESD Alliance panel on September 14th in Silicon Valley, Synopsys loses fully a third of the revenue they’re owed each year for their vast catalog of IP because it’s stolen by Cheaters and used without paying any licensing or royalty fees.
Kelly said Synopsys earns about $200 million per year selling IP, and loses another $100 million to theft. Cheaters are a real problem, he lamented, and as Director of License Compliance for Synopsys he should know. Kelly did not have the floor to share these laments, however, until Warren Savage, GM of IP at Silvaco, opened the meeting.
Speaking from the podium as moderator of the evening’s discussion, Savage said the real problem is the bumblers, those designers and companies who lose track of licensing obligations for IP that was either purchased some time ago, or was brought into the design effort on a data stick fished out of the pocket of someone who’s joined the organization through a poorly managed M&A.
In other words, when Chuckles the Clown uses IP, often as not he doesn’t realize some monies are owed to the third-party IP vendor who created it in the first place. Savage offered this statistic: On an average SoC today, there are 150 to 200 blocks of IP, but only a small percentage of those blocks are actually paid for.
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Tags: Accellera, CAST, Certus, Eric Stein, ESD Alliance, IP fingerprinting, KPMG, PwC, Rob Ballow, Silicon Creations, Silvaco, SoC Solutiosn, Synopsys, The Core Store, True Circuits, Warren Savage
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Thursday, September 8th, 2016
Over the last several weeks, the ESD Alliance has announced two more members, news of particular interest because both companies are IP vendors. C-Sky Microsystems provides 32-bit embedded CPU cores, and Silvaco provides EDA tools for development of analog/mixed-signal devices, power IC and memory design.
True, Silvaco doesn’t sound like an IP vendor until you remember that it just acquired IPextreme, a well-known player in the IP market headed up by Warren Savage. And Savage, now GM of Silvaco’s IP Division, has recently been named chair of the ESD Alliance Semiconductor IP Working Group, tasked with developing a common methodology, best practices for fingerprinting, and solutions for tracking and auditing IP.
Meanwhile, C-Sky Microsystems brings its own unique value proposition to ESD Alliance. Described in the Press Release as “the first IP company from China to join the ESD Alliance,” C-Sky says it intends to actively participate in Savages’ SIP Working Group. This second bit is admirable, but the first could prove complicated.
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Tags: C-Sky Microsystems, Common Platform, ESD Alliance, ESD Alliance Semiconductor IP Working Group, Silvaco, Warren Savage
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Thursday, August 11th, 2016
It’s fantastic to see that the ESD Alliance is following through with its new-found commitment to promote discussion about the IP industry. On Wednesday, September 14th, the Alliance is hosting an evening panel at their headquarters in Santa Clara to discuss semiconductor IP issues that “Keep You Awake at Night”.
As background, consider that the massive amounts of IP involved in building a modern SoC may translate into IP vendors losing millions of dollars if their IP is used therein without proper licensing. At the same time, semiconductor companies also wrestle with troubling issues if their engineers accidentally reuse a core without proper licensing, possibly exposing their employers to huge liabilities. The ESD Alliance event in September promises to address these thorny problems.
Moderated by industry leader Warren Savage – formerly CEO of IPextreme, but now GM of IP at Silvaco with the acquisition announced just prior to DAC – the evening’s two panelists come from interesting backgrounds.
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Tags: Eric Stein, ESD Alliance, IPextreme, KPMG, PwC, Rob Ballow, Silvaco, Warren Savage
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Thursday, July 21st, 2016
Who better qualified to post reactions to this week’s astonishing news out of Tokyo and Cambridge – SoftBank is buying ARM in an all-cash deal for 24.3 billion British pounds – than the leaders of two highly regarded IP companies and an articulate Brit with total street cred in EDA.
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Tags: ARM. SoftBank, Brexit, CAST IP, Dave Kelf, Hal Barbour, Intel, IoT, IPextreme, NXP/Freescale, OneSpin, RISC-V project, TI, Warren Savage
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Thursday, July 14th, 2016
Long-time EDA investor Lucio Lanza lead a fascinating, albeit mystifying, discussion in the DAC Pavilion on Monday, July 6th, in Austin. His panelists included IPextreme’s Warren Savage, Scientific Ventures’ Mark Templeton, and eFabless’ Michael Wishart, with the topic under discussion being open source.
The session was titled “Daring to Move to Open Source” and was described thusly: “The emerging Internet of Things market is destined to upend that time-tested ‘advanced-node’ model, as developers opt for older, less costly process technologies, using commodity design tools and selecting proven IP blocks to quickly and efficiently assemble chips. As demand for IoT devices grows exponentially, might open source EDA tools and IP become viable, or even the winning combination that enables the low-cost design of an IoT SoC?”
Here are some soundbites from the panelists.
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Tags: DAC, Dare to Move to Open Source, eFabless, IPextreme, Lucio Lanza, Mark Templeton, Michael Wishart, Open Source, Scientific Ventures, Silvaco, Warren Savage
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Thursday, May 12th, 2016
IP will be well represented at DAC according to Adapt IP Michael “Mac” McNamara, and he should know. He’s helped build the IP Track at the show and is concerned that everyone understand the IP-related content in Austin this year will be deep and wide.
Mac and I spoke by phone recently. He’d read a blog a posted here in April expressing skepticism about IP coverage at DAC. Therein, I suggested the content set for Austin in June was inadequate, given the important role IP plays in chip design today.
A thoughtful McNamara wanted to respond to this critique; he wanted to evangelize for the quality of the content at DAC – particularly as he is Vice Chair of the conference this year and will be General Chair in 2017. [Cadence’s Chuck Alpert is General Chair here in 2016.]
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Tags: Adapt IP, Anne Cirkel, ARM, DAC 2016, Design Automation Conference, DesignCon, DVCon, ICCAD, IPextreme, Mentor Graphics, Michael McNamara, Synopsys, Warren Savage
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