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Posts Tagged ‘Farzad Zarrinfar’

DAC 2017: Deadlines for IP Submissions start November 15th

Thursday, November 10th, 2016

 


Next Tuesday, November 15th, is the deadline
for submitting research abstracts for the IP track at DAC 2017 in Austin in June. Paper manuscripts are due the following Tuesday. IP-themed session proposals are also due on that Tuesday, November 22nd, while Designer & IP Track proposals are due December 14th.

[NOTE: The December 14th date listed above is for invited Design Track & IP Track proposals. All other proposals for DAC 2017 Design Track & IP Track content can be submitted for review up until January 14, 2017. Thank you to DAC Press Chair Michelle Clancy for this important clarification.]

In other words, if you want to present within the IP Track at the 54th Design Automation Conference, you need to get going now.

The committee that will be overseeing review of these proposals is being headed up by Lattice Semiconductor’s Claude Moughanni – his group taking seriously their role in assembling an IP program that’s both informative and cutting edge.

Moughanni’s committee members include IPnest’s Eric Esteve, Synopsys’ Marc Greenberg, ARM’s Simon Rance, Freescale’s Henning Spruth, Mentor’s Farzad Zarrinfar, Intel’s Ty Garibay, Samsung’s Kelvin Low, Silvaco’s Warren Savage, and Cadence’s Karamveer Yadav – an impressive group who are indeed subject experts.

So, why should you go to all the effort to submit something for review by this group? Is there really any benefit in taking the time to participate at DAC, next year or ever?

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IP @ DAC: Design reuse still not for faint of heart

Thursday, April 16th, 2015

 

Building on last year’s success, the 2015 Design Automation Conference in San Francisco is offering even more substantial content in the track centered on silicon IP and design reuse. Reading through the list of topics, speakers, and companies set to be featured across a diverse set of sessions from June 7-9 at Moscone Center, two things are obvious.

One, a lot of work has been done to assemble all of this. And two, it’s possible the thorny issues surrounding IP reuse may never go away: integration, verifying quality, convincing staff to use design blocks that originate outside of the group, and dealing with the massive amounts of data that IP selection and reuse generates.

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Finally: IP now an Anchor Tenant at DAC!

Thursday, March 20th, 2014

 

Thanks to a lot of hard work and perseverance on the part of various thought leaders in the IP industry – folks like Mike McNamara, Warren Savage, McKenzie Mortensen, Clark Chen, Devin Persaud, Tiffany Sparks, Yervant Zorian, and Farzad Zarrinfar – at last, IP has become an anchor tenant at DAC.

A situation that’s been far too long in coming, given that these days there are approximately 30 companies in the EDA industry, but upwards of 500 in IP.  The fact is, if DAC didn’t make itself available to showcase an industry with 10x more possible exhibitors than EDA, where’s the future of the conference anyway?

I had a chance to speak with ‘Mac’ McNamara on Tuesday of this week about the IP Initiative he’s heading up for DAC 2014. [The others on the list above are on the committee.] Mac’s a legend in the EDA community based on his expertise and leadership roles at Chronologic, SureFire, Verisity and Cadence, where he headed up the company’s C-to-Silicon Compiler and Virtual Systems Platform. Mac left Cadence in 2012, and has served since then as CEO of Adapt IP, an IP startup that boasts both John Sanguinetti and Lucio Lanza on its board.

During our conversation, Mac said that anyone planning on attending the Design Automation Conference this June in San Francisco will want to be there on Monday, June 2nd. That is, anyone who’s interested in the IP industry.

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