Posts Tagged ‘CDNLive’
Thursday, October 26th, 2017
When Cliosoft Founder and CEO Srinath Anantharaman and I spoke recently, it was an energetic conversation. Not surprising, given that the company has 250+ customers worldwide, and exhibits at conferences around the globe.
Adding to the momentum for Cliosoft: In May, the company announced designHUB: “A collaborative IP reuse ecosystem that enables companies to efficiently reuse all types of IP, including semiconductor IP, scripts, PDKs, documents, methodologies, etc. within the company, along with the user experience.”
Anantharaman is clearly enthused about the possibilities designHUB presents for the company’s customers, and is equally enthused about Cliosoft itself.
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Tags: CDNLive, Cliosoft, DAC, Design Reuse, designHUB, IP Reuse Ecosystem, Srinath Anantharaman
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Thursday, November 10th, 2016
Next Tuesday, November 15th, is the deadline for submitting research abstracts for the IP track at DAC 2017 in Austin in June. Paper manuscripts are due the following Tuesday. IP-themed session proposals are also due on that Tuesday, November 22nd, while Designer & IP Track proposals are due December 14th.
[NOTE: The December 14th date listed above is for invited Design Track & IP Track proposals. All other proposals for DAC 2017 Design Track & IP Track content can be submitted for review up until January 14, 2017. Thank you to DAC Press Chair Michelle Clancy for this important clarification.]
In other words, if you want to present within the IP Track at the 54th Design Automation Conference, you need to get going now.
The committee that will be overseeing review of these proposals is being headed up by Lattice Semiconductor’s Claude Moughanni – his group taking seriously their role in assembling an IP program that’s both informative and cutting edge.
Moughanni’s committee members include IPnest’s Eric Esteve, Synopsys’ Marc Greenberg, ARM’s Simon Rance, Freescale’s Henning Spruth, Mentor’s Farzad Zarrinfar, Intel’s Ty Garibay, Samsung’s Kelvin Low, Silvaco’s Warren Savage, and Cadence’s Karamveer Yadav – an impressive group who are indeed subject experts.
So, why should you go to all the effort to submit something for review by this group? Is there really any benefit in taking the time to participate at DAC, next year or ever?
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Tags: 54DAC, AdaptIP, ARM, ARM TechCon, Cadence, CDNLive, Claude Moughanni, Design Automation Conference, Eric Esteve, Farzad Zarrinfar, Henning Spruth, Karamveer Yadav, Kelvin Low, Mac McNamara, Marc Greenberg, Mentor, Simon Rance, SNUG, Synopsys, Ty Garibay, Warren Savage
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Wednesday, August 12th, 2015
Autumn used to start in September, but now classes and conferences commence in August and vacation ends just that much sooner. Here’s a list of various events you should consider attending between now and the end of the year, with thanks to conference organizers for the associated descriptions.
Scanning the range of topics, it’s clear the combined IP and EDA industries have an increasingly broad range of interests: IoT, autos, wearables, software security, verifying/integrating IP, power, device physics, memory, embedded processors and software, sensors, MEMS, a range of standards, networking, both the professional and technical kinds, and “synergistic collaborative design” both up in the cloud and down below on solid ground.
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Tags: 3D ASIP, Aart de Geus, ARC Processor Summit 2015, ARM, ARM TechCon 2015, Autonomous Cars 2015, Cadence, CDNLive, Connect Security World, DVCon Europe, DVCon India, GlobalFoundries, ICCAD 2015, IEDM 2015, Intel Developer Forum, MemCon 2015, Mentor Graphics, Mentor Graphics Forum, PCB West 2015, Si2Con, SMIC, Synopsys, TSMC, TSMC 2015 OIP Ecosystem Forum, Wally Rhines, Wearable Technology Conference
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