Posts Tagged ‘DAC 2016’
Thursday, August 18th, 2016
This is Part 1 of a 5-part discussion of the International Workshop on Design Automation for Cyber-Physical Systems co-located with the Design Automation Conference in Austin in June. Attending this all-day event on Sunday, June 5th, required a commitment of 9 hours and a $200 registration fee, albeit it came with a generous box lunch.
Over the course of the day, 10 speakers expounded on everything from complexity to reliability, from resilience to resource management, from smart buildings to smart grids to smart cars, and threw in a large dollop, as well, of how to deal with those miscreants among us who see opportunities in the emerging world of CPS to do small, medium, and large amounts of harm to our fellow humans and institutions.
Now it’s true, the thought leaders who spoke at CPSDA were consistently articulate, intelligent and well-informed. Nonetheless – even after 9 hours of intense listening, and quite a bit of caffeine – I was still not exactly sure what a cyber-physical system is. So let’s be creative and make up our own definition.
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Tags: CPSDA, DAC 2016, International Workshop on Design Automation for Cyber-Physical Systems
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Thursday, June 2nd, 2016
The first thing to do on Wednesday at DAC 2016 in Austin is take in an hour of the Exhibit Hall. This is the last day for the booths, people are zippy in the morning like horses sensing the stable at the end of their journey, and conversations on the floor are still about the technology. By the end of the afternoon, it’ll be about wistful goodbyes and, “Will we even be here next year when DAC again returns to the Lone Star State?”
Then from 10:30 to noon genuflect to Academia and check out ‘Accelerated Simulation for Circuit Reliability and Stability’. With speakers from Texas A&M, USC, Brown, and Michigan Tech. If you attend, you’ll learn what the future holds for simulation: power supply stability, soft error in logic circuits, thermal noise in ultra-low voltage designs, and the sparsification of spectral graphs used in various design problems. Nobody from industry is speaking, so if you want to get in on the ground floor commercializing some of this stuff, sit in the front row.
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Tags: bagpipes, DAC 2016
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Thursday, May 26th, 2016
There are clearly a lot of collateral distractions at the Design Automation Conference: Networking. Social Hours. Parties. Chotzkies. But the real fun at DAC comes from carving time out to attend technical sessions. This is year in Austin, the offerings are particularly rich.
On Sunday, June 5th, my two favorites are: The Workshop on Design Automation for Cyber-Physical Systems, and The Workshop on Computing in Heterogeneous, Autonomous ‘N’ Goal-Oriented Environments. Both of these all-day events feature experts from academia and industry, most speaking for at least 30 minutes. The topics will be very technical and the schedules allow for detailed presentations. Of course, this doesn’t mean the other workshops on Sunday don’t have great merit, but the two I have identified look to be particularly rich opportunities for learning.
Sunday evening, for the first time, there will also be a 2-hour panel focused on Career Perspectives in EDA, a discussion sponsored by CEDA. Although many will be obliged to attend networking dinners on Sunday evening, or will still be busy setting up booths for Monday morning’s Exhibit Hall opening, attending this Career Panel seems an opportunity not to be missed, particularly as it will be moderated by the supremely knowledgeable Bill Joyner from SRC. Admittedly, this is not a technical session, but the implications for the industry are profound. [File under the heading: ‘Concern for an Aging Industry’]
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Tags: 3D IC, Accellera, Bill Joyner, CEDA, Cyber-Physical Systems, DAC 2016, Design Automation Conference, Edward McCluskey, emulation, Heterogeneous Systems, IoT, Jason Cong, John Sanguinetti, Luca Carloni, Mark Horowitz, Nano-Scale Era, Post Silicon Diagnosis, Power Management, Simulation, UVM
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Thursday, May 12th, 2016
IP will be well represented at DAC according to Adapt IP Michael “Mac” McNamara, and he should know. He’s helped build the IP Track at the show and is concerned that everyone understand the IP-related content in Austin this year will be deep and wide.
Mac and I spoke by phone recently. He’d read a blog a posted here in April expressing skepticism about IP coverage at DAC. Therein, I suggested the content set for Austin in June was inadequate, given the important role IP plays in chip design today.
A thoughtful McNamara wanted to respond to this critique; he wanted to evangelize for the quality of the content at DAC – particularly as he is Vice Chair of the conference this year and will be General Chair in 2017. [Cadence’s Chuck Alpert is General Chair here in 2016.]
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Tags: Adapt IP, Anne Cirkel, ARM, DAC 2016, Design Automation Conference, DesignCon, DVCon, ICCAD, IPextreme, Mentor Graphics, Michael McNamara, Synopsys, Warren Savage
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Thursday, May 5th, 2016
Warren Savage, CEO at IPextreme, is willing to address questions regarding IP content at DAC 2016, enthusiastic in fact. That’s not surprising, given that he serves on the IP Track Committee that reviews the content.
“I think the content’s very good this year,” Savage said in a recent phone call. “We’ve been working on the IP content at the DAC for 3 years, and continue to make progress. I would say the biggest thing [we struggle with] is insufficient time allocated for IP.
“In comparison to previous years, however, the IP and Design tracks have been merged and all put under the same track – something we recommended against, because design-related submissions generally are different from IP-related submissions.”
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Tags: DAC 2016, ESD Alliance, IPextreme, Warren Savage
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