Posts Tagged ‘Accellera’
Thursday, April 27th, 2017
Tom Alsop and the team at Accellera are elated: The UVM standard has been accepted by the IEEE as 1800.2 and congratulations are certainly in order.
The effort has consumed upwards of 10 years, and represents thousands of man-hours of effort, consultation, compromise, consensus building, rinse and repeat. Over and over until the final product was polished, presented and approved by the IEEE. Not an easy process by anybody’s estimation.
When we spoke by phone this week about the Accellera announcement, I asked Tom Alsop [Principal Engineer at Intel] how difficult the whole thing had actually been.
He chuckled slightly: “For us, it was fairly difficult.”
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Tags: Accellera, Accellera Systems Initiative, Cadence, IEEE 1800 SystemVerilog standard, IEEE 1800.2, IEEE Get Program, IEEE Standards Association, Intel, Joe Daniels, Jonathan Goldberg, Justin Refice, Konstantinos Karachalios, Lu Dai, NVIDIA, Stan Krolikoski, SystemVerilog, Tom Alsop, Universal Verification Methodology, UVM, UVM Working Group
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Thursday, September 15th, 2016
Synopsys has a problem. Per Norm Kelly, speaking at the ESD Alliance panel on September 14th in Silicon Valley, Synopsys loses fully a third of the revenue they’re owed each year for their vast catalog of IP because it’s stolen by Cheaters and used without paying any licensing or royalty fees.
Kelly said Synopsys earns about $200 million per year selling IP, and loses another $100 million to theft. Cheaters are a real problem, he lamented, and as Director of License Compliance for Synopsys he should know. Kelly did not have the floor to share these laments, however, until Warren Savage, GM of IP at Silvaco, opened the meeting.
Speaking from the podium as moderator of the evening’s discussion, Savage said the real problem is the bumblers, those designers and companies who lose track of licensing obligations for IP that was either purchased some time ago, or was brought into the design effort on a data stick fished out of the pocket of someone who’s joined the organization through a poorly managed M&A.
In other words, when Chuckles the Clown uses IP, often as not he doesn’t realize some monies are owed to the third-party IP vendor who created it in the first place. Savage offered this statistic: On an average SoC today, there are 150 to 200 blocks of IP, but only a small percentage of those blocks are actually paid for.
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Tags: Accellera, CAST, Certus, Eric Stein, ESD Alliance, IP fingerprinting, KPMG, PwC, Rob Ballow, Silicon Creations, Silvaco, SoC Solutiosn, Synopsys, The Core Store, True Circuits, Warren Savage
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Thursday, May 26th, 2016
There are clearly a lot of collateral distractions at the Design Automation Conference: Networking. Social Hours. Parties. Chotzkies. But the real fun at DAC comes from carving time out to attend technical sessions. This is year in Austin, the offerings are particularly rich.
On Sunday, June 5th, my two favorites are: The Workshop on Design Automation for Cyber-Physical Systems, and The Workshop on Computing in Heterogeneous, Autonomous ‘N’ Goal-Oriented Environments. Both of these all-day events feature experts from academia and industry, most speaking for at least 30 minutes. The topics will be very technical and the schedules allow for detailed presentations. Of course, this doesn’t mean the other workshops on Sunday don’t have great merit, but the two I have identified look to be particularly rich opportunities for learning.
Sunday evening, for the first time, there will also be a 2-hour panel focused on Career Perspectives in EDA, a discussion sponsored by CEDA. Although many will be obliged to attend networking dinners on Sunday evening, or will still be busy setting up booths for Monday morning’s Exhibit Hall opening, attending this Career Panel seems an opportunity not to be missed, particularly as it will be moderated by the supremely knowledgeable Bill Joyner from SRC. Admittedly, this is not a technical session, but the implications for the industry are profound. [File under the heading: ‘Concern for an Aging Industry’]
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Tags: 3D IC, Accellera, Bill Joyner, CEDA, Cyber-Physical Systems, DAC 2016, Design Automation Conference, Edward McCluskey, emulation, Heterogeneous Systems, IoT, Jason Cong, John Sanguinetti, Luca Carloni, Mark Horowitz, Nano-Scale Era, Post Silicon Diagnosis, Power Management, Simulation, UVM
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Thursday, May 19th, 2016
It’s a poorly kept secret that Bob Smith was brought in as Executive Director of EDAC last year to shake things up, to breathe new life into the sails of a somewhat becalmed organization. Well, in the category of be careful what you ask for, here’s how things have gone so far:
New companies have joined the consortium, the newest member of the Board of Directors is not a CEO, a plethora of monthly panels have engaged the industry in thought-provoking discussions about innovation vis-à-vis commercial enterprise, a marketing deal has been struck with Semico, and the whole friggin’ organization has been re-branded as the ESD Alliance to reflect an intent to get more IP guys, more Embedded guys, and more Yet-to-be-identified guys into the alliance than just the traditional anchor tenants from EDA.
But none of this comes close to the potential impact of the latest disruptive idea that ESDA is proposing: The founding of a brand new working group that could very well redefine the whole semiconductor supply chain: The ESD Alliance System Scaling Working Group.
Astonishing.
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Tags: Accellera, Bob Smith, EDAC, ESD Alliance, GSA, Herb Reiter, IEEE, Sematech, Semi, Semico, Si2, System Scaling Working Group
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Tuesday, April 30th, 2013
Bill Martin, President/VP of Engineering at E-System Design, sent a thoughtful response to my April 25th blog regarding Accellera’s recently released Soft IP Tagging 1.0 standard. I appreciate the time he took to clarify the ongoing need for such a standard.
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I was part of VSIA when Kathy Werner was driving the IP tagging standards. I am happy this one from Accellera is now out [Soft IP Tagging 1.0] and the various users can determine how best to apply it. It is a large step forward, but only one of many required.
Unfortunately, the current system for IP tagging can be easily ‘hacked’ to disable any tracking. Simple text editing the source code and removing a few lines can completely remove the tag. But Accellera’s standard is a good first step to hone the standard; understanding how it works and does not work for various constituents.
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Tags: Accellera, Bill Martin, E-System Design, GSA, GSA Interest Group, GSA IP ROI Calculator, IPextreme, Kathy Warner, Soft IP Tagging 1.0 standard, VSIA, Warren Savage
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Thursday, April 25th, 2013
Here’s a rhetorical question regarding Accellera Systems Initiative’s newly announced Soft IP Tagging 1.0 Standard: Is this the holy grail of IP or simply way too much information?
The question seems a fair one given the description in Accellera’s April 15th Press Release: “Normally, control of a third-party IP source is lost once the block of IP is licensed, unlocked, or otherwise made available in clear code. IP Tagging 1.0 facilitates a data-driven method to tag a block of IP and track ‘where used’ for applications such as ownership, royalty calculations, and recognition. It also facilitates the implementation of version identification for applicable bug fixes and errata and allows tracking of other data.”
This last bit, the part where bug fixes can be applied, is clearly the stuff of holy grails. But that first bit – reversing the “normal” loss of control regarding the source of third-party IP after it’s licensed and unlocked – isn’t the stuff of TMI, too much information revealed about something that may be better off kept under wraps?
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Tags: Accellera, Soft IP Tagging 1.0 standard
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