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Peggy Aycinena
Peggy Aycinena
Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at www.aycinena.com. She can be reached at peggy at aycinena dot com.

Apocalypse soon: RISC-V channels mammals after the Asteroid

 
January 19th, 2017 by Peggy Aycinena


At the ESD Alliance panel on the Cadence campus Wednesday night
, it was Vista Ventures’ Jim Hogan who suggested the little open-source processor architecture called RISC-V will prove itself to be a plucky survivor when looming market realities hit 800-pound proprietary vendors like ARM and Intel. Hogan suggested RISC-V is positioned to survive that pending apocalypse just like “the mammals after the asteroid.”

Pretty dramatic stuff.

Hence it should not have been surprising, at the end of the 75-minute discussion on stage between Jim Hogan and Microsemi’s Ted Speers and SiFive’s Yunsup Lee, that I raised my hand and asked why Simon Segars was not in the room. After all, Simon Segars is both CEO of ARM and a key member of the Board of the Alliance that organized the Hogan-Speers-Lee program – a program where the emerging RISC-V movement was described as poised to upend the primacy of ARM etc.

Hogan responded to my question without answering: “Look, ARM is challenging by serving the low-cost processor market. License fees, royalty fees – that is what ARM wants for their low-power edge-based device. I think it was Simon, for example, who started talking to The Street about his economic strategy. It’s not really about what the best technology is, but about the economics. This is what gets the traction, and ARM will respond in an economic way.”

“Yes,” Ted Speers added, “and Intel and Imagination will also respond.”

Respond? Respond to what?

Respond, of course, to the challenge of a free, open-source RISC architecture which is more nimble and better engineered for the needs of the IoT – not to mention providing an antidote to the costs of today’s semiconductor development, which according to Jim Hogan now exceed one hundred million dollars to get product to market.

So back to Simon Segars.

After the formal part of this highly informative evening wrapped up – the panel discussion, 30 minutes of Q&A with a very animated audience, and the occasional dis-embodied input from RISC-V Foundation Executive Director Rick O’Connor calling in from some remote snow-bound location not in Silicon Valley – after all of this formality concluded, everybody got up and moved into the milling-around mode that always wraps up these events.

Everywhere people were chatting with people, and a lot of good humor filled the room. In my corner, I too was chatting with folks when up came a very courteous gentleman. He handed me his business card and announced himself as being Simon Segars’ eyes and ears on the ground.

Olivier Bernard, ARM’s Competitive Strategy Director for the IoT, told me that Simon Segars needn’t have attended the evening’s panel discussion; Olivier would be seeing Simon the next day and would report back to him on everything that had transpired the evening before.

Admittedly amazed, I asked Mr. Bernard, “So you’ve been here in this room the whole time? Even when I raised my hand and asked where the hell is Simon Segars? Why didn’t you raise your hand and make your presence known?”

Olivier smiled and answered easily: “There has always been, and will always be, somebody from ARM at every single RISC-V event. And that’s because we are always partners in innovation. Always.”

Hmm. Okay. Good for them. Who knew?

ARM has eyes and ears everywhere, their finger on the pulse, and their ubiquitous innovative boots on the ground. RISC-V is not catching them by surprise, so we should expect more from their corner as their own nimble and well-engineered technology and team respond to the Little Open Source Processor Architecture that Could.


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Here’s some of what you, or Simon Segars, would have learned between 7 pm and 8:30 pm in Building 10 on the Cadence Campus on Wednesday, January 18th.

Read this list, or wait for the ESD Alliance to post a video record of the discussion on their website.

* RISC-V is growing in popularity and household-name-ness far faster than anyone ever thought it would.

* At last year’s Hot Chips conference, countless people stopped by the RISC-V table to learn what the buzz is all about. The word is out and people are showing extreme levels of interest.

* As an indication of RISC-V’s emerging cache, it was named by the Linley Group as the Best Technology of 2016, even out-polling the very cool FD-SOI.

* The geographical scope and breadth of the appeal of RISC-V is amazing and international. The RISC-V Foundation is going to Shanghai for its next conference, with other international venues scheduled for the coming months.

* The RISC-V Foundation started with 16 companies at the beginning of 2016, but grew to over 100 member companies by the end of the year – an explosive growth in interest around the globe.

* It was UC Berkeley’s Dave Patterson – described by Jim Hogan as “The Father of RISC” – who worked with the group at Cal to name the new architecture RISC-V.

* The “V” in RISC-V is not a “vee” but a “five”.

* Yunsup Lee was a grad student at U.C. Berkeley when he helped develop the RISC-V Instruction Set Architecture. Since finishing his PhD there, he helped start SiFive, now delivering real silicon, very inexpensively, based on RISC-V.

* ARM and Intel built their huge processor companies before security was a problem. Now they’re back-filling to solve security problems. But RISC-V is being built in the here-and-now – with DARPA funding – so it’s benefiting from all the innovation underway around building security into semiconductors.

* Engineering teams in big companies – teams that have access to almost every ISA on the planet, per Ted Speers – are constantly having to deal with the quirks of all of these different instruction sets. What they want is to have just one architecture that will meet all of their needs. This is the promise of RISC-V.

* Although the tools for designing with RISC-V are not yet mature, there’s a road map, there’s up-streaming, and development milestones are being met.

* The RISC-V Foundation has a lot of open source people doing software development. The RISC-V ecosystem is growing rapidly.

* The RISC-V instruction set has been architected to accommodate a lot of extensions. The basic instruction set only has 45 instructions, so users are more than welcome to come in and add their own extensions. They can customize the RISC-V to meet their needs.

* RISC-V will move forward even faster, in lock-step with the exponential growth of the IoT.

* The emerging IoT needs low power at the edge, and although ARM is a great company per Jim Hogan, the economics on the edge of the IoT make very difficult to absorb the cost of an ARM license.

* All of the tension between the IoT, the edge, and the technology needed to support of all of this – RISC-V will solve all of it.

* John Hennessy and Dave Patterson are rewriting their legendary undergrad textbook now based on RISC-V. Therefore engineering student will come up to speed on the architecture while still in school, and will hit the ground running when they enter the work force.

* As Moore’s Law draws to a close, RISC-V will be the driver for the next 50 years of innovation. At last young people have something that’s interesting enough to draw them back into the industry.

* Young mammals are on the move – and they’re moving to RISC-V!

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2 Responses to “Apocalypse soon: RISC-V channels mammals after the Asteroid”

  1. Bill Martin says:

    Peggy,

    ARM is very smart. By telling the audience in advance that a representative was in the room might (really would) have caused a different discussion and to avoid various topics or answers. But by sitting quietly in the room with an unrecognizable ARM representative, ARM was able to see the unadulterated discussion. It will be interesting if Mr. Bernard shows up to any other RISC-V mtgs.

    There are decades of ARM experienced product development engineers that would be critical for a new product’s successful development. ARM has become the de facto standard. Learning a new ecosystem does have costs that can be offset by a non-royalty model. But delays to entering a market can never be caught up.

    It will be interesting to watch RISC-V’s adoption over the next few years.

    Bill

  2. […] more delicious, Arm was in the audience for the RISC-V panel hosted by the ESD Alliance earlier this year. In fact, the Arm rep who attended that event quite […]

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