Posts Tagged ‘RISC-V’
Thursday, December 7th, 2017
This week on Thursday, December 14th, the second annual edition of REUSE 2017 will unfold in Silicon Valley. It’s a gathering crafted specifically for the vendors of IP blocks, and now whole sub-systems, those pieces of the puzzle which allow the vendors’ customers to design and produce electronic products more efficiently and with better results.
It goes without saying that IP is a pivotal part of the semiconductor supply chain today. Organizations like Arm and Synopsys reap huge benefits from being among the principal suppliers of that IP. But there are hundreds of IP companies in the world – big, medium, and small – that also provide IP.
Potentially, they could all be participating in something like Reuse 2017. Arm, for instance, is participating in the conference, along with dozens of smaller companies. Synopsys, however, is not.
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Tags: Achronix, Aldec, Andes Technology, Aphion, Archband, ARM, Avery Design Systems, CAST, Certus Semiconductor, ChipEstimate.com, City Semiconductor, Corigine, DAC, eFabless, FlexLogix, Intel, Intrinsic ID, IP-SoC, Menta, Mixel, Mobile Semiconductor, Mobiveil, Moortec, NSCore, NVM Engines, OmniDesign, Open-Silicon, QuickLogic, Reuse 2017, RISC-V, Samsung, Semi IP Systems, SiFive, Silicon Creations, Silvaco, Sintegra, SmartFlow, Sofics, Sonics, Surecore, Synopsys, True Circuits, Uniquify
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Thursday, November 16th, 2017
Dr. Gabriel Saucier has a lot to be proud of. The Grenoble-based organization she founded, Design and Reuse, is celebrating the 20th anniversary of its flagship conference: IP-SoC.
To celebrate, IP-SoC 2017 is showcasing two of the biggest names in the IP industry – Synopsys CEO Dr. Aart de Geus and ARM founder Sir Robin Saxby. That’s pretty news worthy and a distinct reflection of the significant role Design and Reuse has played for more than two decades in promoting the wide-spread development and reuse of semiconductor IP.
Of course, it’s also worth noting that de Geus and Saxby will not be the only speakers with deep expertise in the technology.
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Tags: Aart de Geus, ARM Holdings, Design-and-Reuse, Gabriel Saucier, Grenoble, IP SoC 2017, RISC-V, Robin Saxby, Synopsys
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Thursday, November 9th, 2017
Simon Segars has been CEO of UK-based ARM Holdings since 2013. When he first joined the company in 1991, he was employee No. 16, and was there when the company went public in 1998.
Last year, Japan-based SoftBank purchased ARM for $32 billion, just a few days after the Brexit vote, and took the company private. This year, SoftBank sold 25-percent of ARM to Saudi Arabia, in a deal that was part of the company’s (and kingdom’s) Vision Fund juggernaut.
Simon Segars has more than survived all of this change. He is still CEO of the most ubiquitous IP provider in the world, and now also has a seat on the Board of Directors of SoftBank.
As I prepared for my phone call with Segars last week, I was pretty sure he would decline to answer the bulk of the questions on my list. Surprisingly, however, he answered all of them, with ease and on the record. We started with the most astonishing news of all: ARM has changed its name.
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Tags: Advanced RISC Machines, ARM Holdings, ARM TechCon, Bob Gardner, EDA Consortium, ESD Alliance, Masayoshi Son, RISC-V, Saudi Arabia, Simon Segars, SoftBank, SoftBank Vision Fund
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Thursday, November 2nd, 2017
U.C. Berkeley Prof. Alberto Sangiovanni-Vincentelli has just been named non-Executive Chairman of UltraSoC, an IP provider based in Cambridge. He was in Rome when we spoke this week by phone about the news.
UltraSoC CEO Rupert Baines was also on the conference call, dialing in from the UK, while I was in Silicon Valley. The conversation began with a discussion of Sangiovanni-Vincentelli’s ongoing research work in Singapore.
Three sentences, four geographies: What more proof is needed that the semiconductor industry is indeed global?
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Tags: Alberto Sangiovanni-Vincentelli, Atlante Ventures, Cadence, CEVA, Coadasip, Elvees, HiSilicon/Huaweei, Imagination, ISO 26262, Lauterrbach, MIT, Movidius, Netspeed, NRF CREATE, RISC-V, Rupert Baines, SiFive, Singapore, Sondrel, Synopsys, Technical University of Munich, U.C. Berkeley, UltraSoC
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Thursday, June 15th, 2017
UltraSoC is on a roll, having just wrapped up an energetic participation in the last month’s RISC-V conference in Shanghai, where UltraSoC CTO Gadge Panesar was a speaker. Additionally, the company is announcing “new funding, new investors, and new board members” – including UC Berkeley’s Alberto Sangiovanni-Vincentelli.
When I spoke this week with company CEO Rupert Baines, he started with Shanghai: “There is so much interest in RISC-V in China. The attendance there [exceeded] the headcount at the previous meetings at Google and MIT, although the numbers may be confusing as there were so many students at the Shanghai event.”
Asked if the RISC-V event would be in China again, Baines said, “I believe going forward there will be one conference in the U.S. each year, probably in Silicon Valley, and one international. Nvidia sponsored the latest one through their presence in Shanghai.”
Turning to UltraSoC, I asked about the company’s origin, market and competition.
Baines said, “We do semiconductor IP that solves a problem. The chips are so big and complicated today, understanding how they work – with lots of processors and lots of software interacting with each other and the real world – is incredibly difficult.
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Tags: Alberto Sangiovanni-Vincentelli, ARM, ARM TechCon, CEVA, Design Automation Conference 2017, Gadge Panesar, HiSilicon, Imagination, Microsemi, MIPS, Movidius, RISC-V, Rupert Baines, Tensilica, UltraSoC
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Thursday, January 19th, 2017
At the ESD Alliance panel on the Cadence campus Wednesday night, it was Vista Ventures’ Jim Hogan who suggested the little open-source processor architecture called RISC-V will prove itself to be a plucky survivor when looming market realities hit 800-pound proprietary vendors like ARM and Intel. Hogan suggested RISC-V is positioned to survive that pending apocalypse just like “the mammals after the asteroid.”
Pretty dramatic stuff.
Hence it should not have been surprising, at the end of the 75-minute discussion on stage between Jim Hogan and Microsemi’s Ted Speers and SiFive’s Yunsup Lee, that I raised my hand and asked why Simon Segars was not in the room. After all, Simon Segars is both CEO of ARM and a key member of the Board of the Alliance that organized the Hogan-Speers-Lee program – a program where the emerging RISC-V movement was described as poised to upend the primacy of ARM etc.
Hogan responded to my question without answering: “Look, ARM is challenging by serving the low-cost processor market. License fees, royalty fees – that is what ARM wants for their low-power edge-based device. I think it was Simon, for example, who started talking to The Street about his economic strategy. It’s not really about what the best technology is, but about the economics. This is what gets the traction, and ARM will respond in an economic way.”
“Yes,” Ted Speers added, “and Intel and Imagination will also respond.”
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Tags: ARM, Dave Paterson, ESD Alliance, Imagination Technologies, Intel, Jim Hogan, John Hennessy, Linley Group, Microsemi, Olivier Bernard, Rick O'Connor, RISC-V, RISC-V Foundation, SiFive, Simon Segars, Stanford, Ted Speers, U.C. Berkeley, Vista Ventures, Yunsup Lee
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Thursday, January 5th, 2017
One of your New Year’s Resolutions should be to further understand the philosophy, technology, and implications of the RISC-V movement. And there will be no better way to follow through on that resolution than to attend the upcoming ESD Alliance discussion on the topic.
In a nod to the best in situational irony, the Alliance is hosting an evening event in Silicon Valley on January 18th specifically to discuss this open source processor architecture, which per some has the potential to turn ARM’s market dominance on its ear.
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Tags: ARM, BSD License, DAC, Dave Patterson, ESC Boston, ESD Alliance, Google, IoT Meetup, Jim Hogan, Krste Asanovic, MIT, Oracle, Rick O'Connor, RISC-V, RISC-V Foundation, SiFive, U.C. Berkeley, Yunsup Lee
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