Posts Tagged ‘Synopsys’
Monday, May 6th, 2019
Sanjay Gangal interviewed Rita Horner, Senior Technical Marketing Manager of Synopsys at EDACafe headquarteers.
SG: You attended the IP-SOC conference here yesterday, and you did a presentation there.
RH : Yes, we had a very interesting day yesterday at IP-SOC.
SG: Tell us what was your presentation was about.
RH : I presented on the 400G adoption, and the new networking data centers enabled by the 56G PHY. That was the topic of the presentation that I made yesterday.
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Tags: 400G, PHY, Synopsys 1 Comment »
Thursday, December 7th, 2017
This week on Thursday, December 14th, the second annual edition of REUSE 2017 will unfold in Silicon Valley. It’s a gathering crafted specifically for the vendors of IP blocks, and now whole sub-systems, those pieces of the puzzle which allow the vendors’ customers to design and produce electronic products more efficiently and with better results.
It goes without saying that IP is a pivotal part of the semiconductor supply chain today. Organizations like Arm and Synopsys reap huge benefits from being among the principal suppliers of that IP. But there are hundreds of IP companies in the world – big, medium, and small – that also provide IP.
Potentially, they could all be participating in something like Reuse 2017. Arm, for instance, is participating in the conference, along with dozens of smaller companies. Synopsys, however, is not.
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Tags: Achronix, Aldec, Andes Technology, Aphion, Archband, ARM, Avery Design Systems, CAST, Certus Semiconductor, ChipEstimate.com, City Semiconductor, Corigine, DAC, eFabless, FlexLogix, Intel, Intrinsic ID, IP-SoC, Menta, Mixel, Mobile Semiconductor, Mobiveil, Moortec, NSCore, NVM Engines, OmniDesign, Open-Silicon, QuickLogic, Reuse 2017, RISC-V, Samsung, Semi IP Systems, SiFive, Silicon Creations, Silvaco, Sintegra, SmartFlow, Sofics, Sonics, Surecore, Synopsys, True Circuits, Uniquify No Comments »
Thursday, November 16th, 2017
Dr. Gabriel Saucier has a lot to be proud of. The Grenoble-based organization she founded, Design and Reuse, is celebrating the 20th anniversary of its flagship conference: IP-SoC.
To celebrate, IP-SoC 2017 is showcasing two of the biggest names in the IP industry – Synopsys CEO Dr. Aart de Geus and ARM founder Sir Robin Saxby. That’s pretty news worthy and a distinct reflection of the significant role Design and Reuse has played for more than two decades in promoting the wide-spread development and reuse of semiconductor IP.
Of course, it’s also worth noting that de Geus and Saxby will not be the only speakers with deep expertise in the technology.
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Tags: Aart de Geus, ARM Holdings, Design-and-Reuse, Gabriel Saucier, Grenoble, IP SoC 2017, RISC-V, Robin Saxby, Synopsys No Comments »
Thursday, November 2nd, 2017
U.C. Berkeley Prof. Alberto Sangiovanni-Vincentelli has just been named non-Executive Chairman of UltraSoC, an IP provider based in Cambridge. He was in Rome when we spoke this week by phone about the news.
UltraSoC CEO Rupert Baines was also on the conference call, dialing in from the UK, while I was in Silicon Valley. The conversation began with a discussion of Sangiovanni-Vincentelli’s ongoing research work in Singapore.
Three sentences, four geographies: What more proof is needed that the semiconductor industry is indeed global?
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Tags: Alberto Sangiovanni-Vincentelli, Atlante Ventures, Cadence, CEVA, Coadasip, Elvees, HiSilicon/Huaweei, Imagination, ISO 26262, Lauterrbach, MIT, Movidius, Netspeed, NRF CREATE, RISC-V, Rupert Baines, SiFive, Singapore, Sondrel, Synopsys, Technical University of Munich, U.C. Berkeley, UltraSoC No Comments »
Thursday, October 5th, 2017
Hangzhou C-SKY Microsystems, a 32-bit CPU vendor, became a member of the ESD Alliance in 2016 and was described at the time as “the first IP company from China to join.”
Founded in 2001, C-Sky has “developed 7 types of embedded CPUs covering a wide range of embedded applications including smart devices in IoT, digital audio and video, information security, network and communications, industrial control and automotive electronics. It is the only embedded CPU volume provider in China with its own instruction set architecture, the Yun-on-Chip architecture developed in conjunction with Alibaba.”
C-Sky is a growing IP company serving an enormous market. I spoke recently by phone with Dr. Xiaoning Qi, CEO at C-Sky, who was in California attending meetings. No stranger to Silicon Valley, he previously served at Intel, Rambus, Synopsys, and Sun, after completing his Ph.D. under Prof. Robert Dutton at Stanford.
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Tags: Aart de Geus, Alibaba, ARM, Asia-Pacific Leadership Council, Bob Smith, C-Sky Microsystem Corp., Chenming Hu, Chi-Foon Chan, Chinese American Semiconductor Professional Association, ESD Alliance, GSA, IEEE, Intel, Mentor Graphics, Microsoft, NB-IoT, Rambus, Robert Dutton, SMIC, Stanford, Subhasish Mitra, Sun Microsystems, Synopsys, TSMC, Wally Rhines, Xiaoning Qi, ZTE 1 Comment »
Thursday, September 28th, 2017
Sage Design Automation offers iDRM – integrated design rule management – a “true design rule compiler that enables quick graphical capturing of design rules and uses them as executable expressions for Specification, Communication, Validation, DRC, Analysis, Deck validation and coverage, and DRC deck generation.”
But this is not about Sage, it’s about how Sage fits into an evolving industry from the point of view of Raul Camposano, EDA veteran, former CTO at Synopsys, and currently CEO at Sage. Like so many serving in leadership roles in the industry, Dr. Camposano is a man of good cheer and an optimistic observer.
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Tags: Dan Nenni, DRC decks, ESD Alliance, Giovanni De Micheli, IoT, Kurt Keutzer, Mead Conway, Mentor Graphics, Moore's Law, Raul Camposano, Sage, Silicon Catalyst, Synopsys, TSMC 4 Comments »
Thursday, June 8th, 2017
This is fourth in a 4-part series on Grand Challenges in IP. Previous dialogs featured Sonics CEO Grant Pierce, CAST-IP Board Chair Hal Barbour, and Silvaco IP Division GM Warren Savage. This final, lengthy conversation is with Synopsys co-CEO Aart de Geus, winner of the 2008 Phil Kaufman Award.
To say Aart de Geus is synonymous with Synopsys, an organization he’s led for over 30 years, is not an understatement. His entire professional zeitgeist is wrapped up in the company. Neither is it an understatement to say de Geus is always on-message, always on-point. The interview below is no exception.
Dr. de Geus’ vision of Grand Challenges in IP is informed by the daily, working realities of the needs of the customers that constitute the IP market, and an IP vendor’s evolving response to those needs. We spoke by phone on June 1st.
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Tags: Aart de Geus, Grand Challenges in IP, Moore's Law, Synopsys No Comments »
Thursday, May 25th, 2017
This conversation with Hal Barbour, Chairman at CAST IP, is the second of four dialogs about Grand Challenges in IP.
The first installment in the series, published last week, was a conversation with Sonics co-Founder and CEO Grant Pierce.
Pierce argues that today’s Grand Challenges in IP center around the complexities of delivering sub-systems and related technical expertise to customers, helping develop edge-node devices targeted at Machine Learning, and providing IP for myriad automotive systems – all while meeting demands for greater bandwidth and throughput, and astonishingly low power.
In this week’s installment in the series, Hal Barbour talks about a completely different set of Grand Challenges in IP – those related to the business issues surrounding the industry.
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Tags: ARM, Beyond Semiconductor, Cadence, CAST IP, Fraunhofer Institute, Hal Barbour, Mentor Graphics, Nikos Zervas, Ocean Logic, Paul Lindemann, Sandgate, Silesia Devices, SoC Solutions, SoftBank, Synopsys, View Logic 1 Comment »
Thursday, April 13th, 2017
Something eerie and inexplicable happened on Thursday evening, April 6th. Out of nowhere, an intense storm swept through the Bay Area, unannounced and without warning. The skies darkened, the winds howled, severe rain pelted the crowded, suddenly dangerous freeways, and hundreds of thousands lost power.
Meanwhile, exactly in the midst of the most violent part of this mysterious storm, the CEOs of the four most important companies within the ESD Alliance sat on stools in front of an audience assembled at Synopsys and chatted about this, that, and the other. Seemingly oblivious to the profound violence unleashing itself just outside the windows, they acted as if nothing was amiss.
Everything in the industry – and the world – was in order: Wonderful, with the data pointing continuously up and to the right, and everywhere ample evidence for a bullish, optimistic, and excited outlook on the future of EDA and IP.
No matter that Nature was having its way out there in the darkness, that the U.S. had bombed Syria the hour before their discussion began, that the drumbeat for answers about entanglements with Russia was quickening, or difficult conversations with the President of the PRC were underway that very day in Florida – the CEOs of Synopsys, Cadence, Siemens/Mentor Graphics and SoftBank/ARM sat relaxed and easy, basking in the evident vitality of the EDA and IP industries, and allowing themselves to be shepherded through a congenial confab of confident chit-chat by Ed Sperling of Semiconductor Engineering fame.
That fact that the vagaries of Nature never came into the conversation was not surprising; the fact the Mr. Sperling refused all opportunities to bring what he termed as “politics” into the conversation was quite the opposite. Surprising, that is.
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Tags: Aart de Geus, ARM, Brexit, Cadence, Ed Sperling, ESD Alliance, H1-B visas, Lip-Bu Tan, Mentor Graphics, Semiconductor Engineering, Siemens, Simon Segars, SoftBank, Synopsys, Walden C. Rhines 2 Comments »
Thursday, March 16th, 2017
It takes skill and surgical precision to launch and maintain a tech startup, especially today and extra-especially in a market as competitive as IP. Nonetheless, Massachusetts-based Performance-IP seems to have accomplished that feat.
It’s true, this is not the first IP company co-founded by Performance-IP CTO Gregg Recupero. In the early 1990’s, he helped to found VAutomation which developed IP for system-level verification [and was acquired by ARC in 2000].
In our phone call this week, I asked Recupero how a small IP company today can compete with the behemoth IP providers.
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Tags: Cadence, Gregg Recupero, Performance-IP, Synopsys, VAutomation No Comments »
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