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Peggy Aycinena
Peggy Aycinena
Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at She can be reached at peggy at aycinena dot com.

Performance-IP: Finding a Different way to Compete

March 16th, 2017 by Peggy Aycinena

It takes skill and surgical precision
to launch and maintain a tech startup, especially today and extra-especially in a market as competitive as IP. Nonetheless, Massachusetts-based Performance-IP seems to have accomplished that feat.

It’s true, this is not the first IP company co-founded by Performance-IP CTO Gregg Recupero. In the early 1990’s, he helped to found VAutomation which developed IP for system-level verification [and was acquired by ARC in 2000].

In our phone call this week, I asked Recupero how a small IP company today can compete with the behemoth IP providers.

He started by referencing his earlier experience: “At VAutomation, we started doing synthesizable logic and as a side project, made behavioral RTL synthesizable in response to a request from a customer.

“At the time, we were developing x86 microprocessors, and also standards-based IP – Ethernet, PCI, USB – the kind of thing that makes it tough for IP companies to compete today with the behemoths.”

“When you develop standards-based IP,” Recupero noted, “you compete on price. But how can a small IP company do that today up against a Synopsys or a Cadence, companies that offer a complete suite of IP, tools and technology?”

It was that consideration which informed Recupero’s decision, ten years after leaving ARC to work in various engineering settings, to become involved with Performance-IP.

“It was completely different from what I did at VAutomation,” Recupero said. “With Performance-IP, we have technology that differentiates us from the competition.

“The technology is innovative, unique, and something that Synopsys or Cadence doesn’t offer in their suites. And it’s patented.”

“What’s particularly nice about the technology,” he added, “it can actually improve the performance of the IP that Cadence or Synopsys offers, so there’s good synergy between what we provide and IP from the larger companies.

“The flagship product that Performance-IP offers actually connects seamlessly to a Cadence or Synopsys DDR controller, and can give the customer a large reduction in latency, a 10-to-20 percentage improvement in performance.”

Does this put your company on the radar of Synopsys or Cadence, I asked.

Recupero chuckled and said, “Yes, I would think so.

“We’ve been around for quite a while, working with customers involved in the ADS [autonomous driving systems] and ML [machine learning] space – things that need high computation and a lot of throughput for the processors.

“Even customers wanting to improve performance on their flash memory are having success with our MRO – Memory Request Optimizer – formally announced this week.

“With MRO and our other two products, L2+ Cache and HP-DMA Controller, we cover the spectrum of the customers’ needs. And again, the technology is memory-standards independent and can help all classes of memory.”

The company seems very well positioned to compete in today’s market, I noted.

“Thanks, we are,” Recupero responded.

“We’ve been working on all of this for quite a while, and knew to spend the time at the outset to get things patented, as I mentioned. A process that took over a year.”

How did the company keep the lights on during that time?

“We engaged with early adopters to accomplish that,” he said, “using the same bootstrapping technique I used at VAutomation. Finding key customers that understood us and helped us get into production, while still allowing us to retain full control.

“This has always been very important, to have control over the products we’re developing and who we work with in that process.”

So Performance-IP is an outlier in three different ways, I suggested: It’s a startup, it’s competing in the IP market, and it’s bootstrapped.

Recupero responded, laughing, “Yes, we like to make it as hard as possible. And we’re trying to keep everything that worked well with VAutomation. We’ve also been able to do a lot of our marketing online.

“But most importantly, we continue to pride ourselves on our customer support. It’s always been 100-percent support, with prompt response to all customer questions. Always going above and beyond what we need to do to support them.

“Our being so responsive has helped us to not have to visit our customers as much in person, although we are gearing up to do a series of Tech Days. Our first one is coming up in Israel in the spring, working through our distributor there.”

“Going back to your original question about competing in the IP market today,” Recupero concluded, “we are succeeding by doing things differently.

“It’s true, it’s not easy to start an IP company, but through a lot of hard work and constant attention to the customer, we are proving that it can be done.

“If you have a product that can technically differentiate itself from what the other companies offer, you can be successful today.”


March 15 Press Release …

BOSTON, MA – Performance-IP today introduced Memory Request Optimizer (MRO) to deliver improved memory efficiency and increase the performance of an SoC. MRO reduces memory latency between the memory subsystem and the SoC client – CPU, GPU, codec or video processor, for example – by providing on-demand data delivery and increasing the bandwidth between the two. Its unique programmable memory optimization capability offers in-system analysis to dynamically reconfigure an SoC’s power and performance profile.

“Most memory subsystems operate at less than 80% efficiency,” says Gregg Recupero, CTO of Performance-IP. “The inefficiency slows the pipeline performance of the communications to and from the SoC client to the memory, even as new memory standards demand more efficiency from the memory. This needed to be improved dramatically.”

MRO supports industry standard AXI4 and OCP on-chip interconnect specification protocol interfaces for a seamless connection to memory controllers or any other SoC client. It is delivered as a block of silicon intellectual property (IP) that can be integrated easily into an SoC’s design. It can reside at any point in memory hierarchy while connecting directly to existing client and memory controllers.


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