Posts Tagged ‘Synopsys’
Thursday, August 1st, 2013
Bill Martin, President/VP of Engineering at E-System Design, has sent another thoughtful response to a blog regarding IP, in particular my post last week about the astonishing increase in the valuation of ARMH over the last 5 years.
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Years ago, Chris Rowen had a clear vision where EDA and IP would start to merge, given the complexities of both. He knew both could have a large impact on the resources and risks associated with creating an SoC. His vision was so compelling, Chris resigned from a great group within Synopsys to form his start-up, Tensilica.
At the time, EDA/IP/Customization were all difficult problems to resolve. By building larger blocks that automatically reconfigured and combined other aspects (examples: SW compiler/debugger for code that could add/delete instructions and a verification suite that reconfigured themselves based customers’ usage), the solution Chris created at Tensilica addressed SIP/Embedded SW/VIP and EDA.
Quite an ambitious undertaking, but over time as his solution was honed and matured, the industry saw the end result – a few months ago the large acquisition of Tensilica by Cadence. In fact, the deal was part of a trend. Look at the various EDA and IP acquisitions since 2008, those exceeding $100 million:
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Tags: Ansoft, Apache, ARM, Bill Martin, Cadence, Chris Rowen, Denali, E-System Design, IPextreme, Magma, Synopsys, Synplicity, Tensilica, VirageLogic
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Thursday, June 20th, 2013
Despite their marked contributions to DAC in Austin, the folks in the IP world have not been resting on their laurels, but have continued to generate developments of both a technical and business nature.
** Synopsys and OCZ Technology Group announced OCZ “achieved first-pass silicon success” in its newest NAND flash Vector SSD using Synopsys’ DesignWare DDR2/3-Lite PHY, Embedded Memories, STAR Memory System, and Professional Services.
The companies say the OCZ Vector SSD was designed “to deliver superior sustained performance through its new, high-performance Indilinx Barefoot 3 flash controller supporting the SATA-3 protocol. Synopsys’ design consultants worked closely with OCZ’s engineers throughout the implementation of their chip, delivering expertise and advanced methodologies in IP integration, physical design, and physical verification that enabled OCZ to complete their implementation in less than six months.”
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Tags: Andes Technology, Arasan, ARM, BDA, Beyond Semiconductor, Cadence Design Systems, CAST, Cavium, eMemory Technology, Evatronix, GDA Technologies, Imagination Technologies, MIPS, Mixel, NVIDIA, OCZ Technology Group, Synopsys
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Thursday, May 30th, 2013
** IPextreme announced it will collaborate with its Constellations program members and other key players in the semiconductor IP ecosystem to host the Stars of IP Party on June 4th, an event coinciding with DAC 2013 in Austin, Texas. The company says Stars of IP celebrates “all things semiconductor IP” and seeks to build relationships among IP provider companies and customers, thereby strengthening the ecosystem. Co-hosting with IPextreme are Atrenta, CAST, Certus Semiconductor, Recore Systems, Sonics, Synopsys, and True Circuits.
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Tags: Alma Technologies, ARM, Atrenta, Brett Cline, Cadence Design Systems, CAST, Certus Semiconductor, Charlie Cheng, CircuitSutra, Constellations, Cosmic Circuits, DAC 2013, Forte Design Systems, Grant Pierce, IPextreme, Kilopass Technology, Martin Lund, Michael Mo, Recore Systems, S.C. Chien, Sonics, Synopsys, True Circuits, UMC, Umesh Sisodia
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Thursday, April 4th, 2013
Despite grumbling to the contrary, even some that I myself put forth in a blog earlier this year, there will indeed be a daily dose of IP information doled out at DAC in Austin in June. If you’re interested in IP, DAC 2013 actually promises to be quite informative. You can arrange your schedule so as to attend a single significant session each day devoted to various aspects of IP with all of its promise and particulars.
Here’s your DAC planning guide …
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Tags: Arteris, Atrenta, Chris Rowen, DAC 2013, Dan Kochpatcharin, David Murray, Duolog Technologies, Frank Ferro, Freescale, Hans Bouwmeester, IPextreme, John Eaton, John Swanson, Jose Nunez, Kamlesh Kumar Pathak, Keith Odom, Laurent Moll, Magillem Design Services, McKenzie Mortensen, Michael Cizi, Mike Gianfagna, Nagendra Gulur, National Instruments, Open-Silicon, Ouabache Designworks, Sonics, Southwest Reuse, STMicro, Sylvain Duvilliard, Synopsys, Tensilica, TI, TSMC, Vasant Kumar Easwaran, Warren Savage
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Thursday, March 21st, 2013
If you thought about going to the Synopsys Users Group meeting next week in Silicon Valley, there’s at least one topic that would make it worth your time: This week ARM and Synopsys announced “optimized 28-nm Synopsys Reference Implementations for ARM Cortex-A15 MPCore and Cortex-A7 MPCore processor clusters, as well as the CoreLink CCI-400 cache-coherent interconnect.”
The reference implementations are currently available, and include “scripts, floorplan, constraints and documentation” – scripts that are built on Synopsys’ tool Reference Methodologies and are optimized for high-performance cores. Clearly attending SNUG would clarify what you need to know to use all of this, but first apparently you need to understand ARM’s big.LITTLE processing. Which is what?
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Tags: ARM, ARM big.LITTLE processing, SNUG, Synopsys, Synopsys Reference Implementations
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Tuesday, March 12th, 2013
As the trading day in New York draws to a close, it would appear that some analysts are correct; the market’s not too pleased about yesterday’s announcement that Cadence is acquiring Tensilica. Shares of CDNS are trading down well over 3% today. But you know, the market’s stupid. They understand zip zero nada about EDA or IP, and really why should they?
After all, EDA and IP providers make the black magic that they do look so easy. And, they’re constantly telling people that what they do isn’t rocket science. But it is! The EDA vendors make the tools that IP vendors use to create their products, and designers use to integrate said IP into the larger designs. It’s called an eco-system and it is rocket science.
It’s also on the level of brain surgery, quantum physics, and a bunch of other esoteric science and engineering disciplines that require a lot of education and and a lot of OJT, and even then is really hard to do. How many traders on Wall Street, or the analysts who track it all, really understand what EDA and/or IP are all about? Exactly!
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Tags: ARM, Cadence, CDNS, Chris Rowen, EDAC CEO Panel, Lip-Bu Tan, Simon Segars, Synopsys, Tensilica
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Thursday, February 28th, 2013
If you’re free on the evening of Thursday, March 14th, you should plan on attending EDAC’s annual CEO Forecast Panel. It promises to be full of executive content, albeit perhaps a bit light on forecast content, but oh well. That’s the nature of life in the Publicly Traded Fast Lane these days.
Along with the CEOs of Mentor Graphics, Cadence, Synopsys, and Nimbic, the president of ARM will also be on stage, Simon Segars. Segars is no stranger to public speaking. You can hear his recent ARM TechCon 2012 keynote here. But it’s not what Segars will say on stage at the DoubleTree Hotel in San Jose on March 14th that matters. It’s his body language, and you’ll only be able to read that if you’re in the room.
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Tags: Aart de Geus, ARM, Cadence, EDAC, EDAC CEO Panel, Lip-Bu Tan, Mentor Graphics, Nimbic, Raul Camposano, Rich Valera, Simon Segars, Synopsys, Wally Rhines
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Thursday, February 14th, 2013
After the euphoniously monikered IP provider, Uniquify, announced several weeks ago that the more whimsically monikered organization, Pixelworks, is using Uniquify’s DDR memory controller subsystem IP for multiple distinct processors that Pixelworks is, in turn, providing to TV makers who make 4Kx2K ultra high-def systems, one question still remained: How did Pixelworks know to use Uniquify’s offering?
According to a January 2013 article in IEEE Spectrum, knowing what IP to use in a project here in the 21st century is fairly easy knowledge to come by. I don’t know what planet the author of the op-ed piece, “Other People’s Knowledge”, lives on but it doesn’t seem to be the one that I hear about from the folks who make or buy third-party IP.
In fact, those people seem to indicate that knowing what IP to use in a particular project continues to be far more art than science. In particular, because until a system, or sub-system, is fully defined, modeled and simulated – let alone, manufactured and deployed in the field – one can never really know how a piece of IP is going to work in the environment into which it’s been placed.
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Tags: BarcoSilix, Cadence, DDR memory controller IP, Eureka Technology, IP, Synopsys, TI, Uniquify, Xilinx
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Thursday, September 27th, 2012
Over the last several months, Synopsys has made multiple announcements aggressively proving their ongoing presence in the burgeoning IP market: Silicon IP, Verification IP, and ARM-based design. Meanwhile, through community outreach, Synopsys has also continued to enhance the most important category of intellectual property: students in local schools.
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Tags: ARM, DesignWare IP, HItachi, Lee Mathson Middle School, MIPI Alliance, SIP, Synopsys, Synopsys Foundation, VIP
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Tuesday, September 18th, 2012
Chris Rowen is Founder and CTO of Tensilica, an IP company based in Silicon Valley. We spoke last week by phone to discuss how an IP company decides what and when to introduce new products.
I first asked to Chris for a brief history of the RISC [Reduced Instruction Set Computing] architecture he is closely associated with, and how that history segued into the founding of Tensilica.
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From RISC to Tensilica …
Q: Can you give me a quick overview of the origins of RISC architecture?
 Chris Rowen: RISC is a set of ideas that grew up in academia and IBM in response to increased architectures in both the mainframe and microprocessor worlds.
People saw machines with really high hardware costs being built for assembly [language applications]. However, as compiler technology got better, people said: If I want a compiler to run well, I don’t need fancy instructions. I only need a common set of instructions that run really fast. All other complex operations could be composed by the compiler out of these fast, simple operations.
RISC grew out of these compiler technology advances, and a recognition in the VLSI era that there was an opportunity to rethink the process of how the architecture could be put together. (more…)
Tags: ARM, Chris Rowen, Dave Patterson, IBM, John Cocke, John Hennessy, MIPS Computer Systems, RISC, Silicon Graphics, Stanford, Synopsys, Tensilica, U.C. Berkeley
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