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Peggy Aycinena
Peggy Aycinena
Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at She can be reached at peggy at aycinena dot com.

Synopsys: Writing the book on IP

September 27th, 2012 by Peggy Aycinena

Over the last several months, Synopsys has made multiple announcements aggressively proving their ongoing presence in the burgeoning IP market: Silicon IP, Verification IP, and ARM-based design. Meanwhile, through community outreach, Synopsys has also continued to enhance the most important category of intellectual property: students in local schools.

Silicon IP …

* September 5th: Synopsys announced the 100th design win of its DesignWare IP optimized for 28-nm processes for multiple leading foundries. Synopsys’ 28-nm DesignWare IP has been silicon-characterized across process, voltage and temperature variations in both High-K Metal Gate and PolySiON technologies for design robustness; the portfolio includes PHYs for USB, PCI Express, SATA, HDMI, DDR, MIPI, as well as data converters, audio codecs, embedded memories and logic libraries. To date, 30+ test chips in 10+ different 28-nm process nodes have taped out, with products shipping in volume.

* September 18: Synopsys announced expansion of its DesignWare DDR interface IP portfolio to include support for next-generation SDRAMs based on the emerging DDR4 standard. By supporting DDR4 as well as DDR3 and LPDDR2/3 in a single core, the DesignWare DDR products allow designers to interface with either high-performance or low-power SDRAMs in the same SoC.

* September 24: Synopsys announced availability of the DesignWare MIPI UniPro Controller for host and device storage, camera and display applications, and the DesignWare UFS Host Controller for storage applications. The new IP works in tandem with the multi-gear DesignWare MIPI M-PHY IP to speed implementation of the MIPI Alliance UniPro and UFS interface standards in application processors, mobile systems-SoCs and peripheral ICs.

Verification IP …

September 19: Synopsys announced that the storage solutions division of Hitachi, Ltd. has selected Synopsys’ Discovery Verification IP for the ARM AMBA AXI3 protocol for verification of Hitachi Virtual Storage Platform.


August 28: ARM and Synopsys signed a multi-year agreement that expands Synopsys’ access to a range of ARM IP. The two companies are broadening their collaboration to optimize ARM technology-based SoCs with Synopsys Galaxy Implementation Platform and Discovery VIP. Synopsys will now have access to a range of Cortex processors, including technology needed to implement ARM big.LITTLE processing, ARM Artisan physical IP, POP technology optimized for Cortex processor implementation, as well as CoreLink interconnect and AMBA 4 ACE system IP.  Synopsys will be able to create optimized tools and methodologies for the implementation and verification of ARM processing subsystems, and ARM will be able to enhance its IP.

Human IP …

September 20: Synopsys announced that the Synopsys Silicon Valley Science and Technology Outreach Foundation has reached a major milestone of providing more than one million unique experiences to students and teachers developing science projects since the program’s inception in 1999. Experiences include support for science project development, science fair sponsorship, competitions and teacher training offered through a range of Foundation programs. A group of Santa Clara County teachers joined Synopsys executives and Foundation board members to mark the milestone at a reception on September 24th at the Computer History Museum in Mountain View.

June 23rd: Synopsys Headquarters celebrated its 25th anniversary by refurbishing Lee Mathson Middle School in San Jose. In partnership with City Year, more than 500 Synopsys employees, their families and friends, along with Lee Mathson community members (parents, teachers & students) joined together to repaint buildings, build benches, plant a garden, paint murals and more.

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