Posts Tagged ‘Synopsys’
Wednesday, November 18th, 2015
This week Synopsys announced “unauthorized third-party access to Synopsys EDA, IP and optical products and product license files through its customer-facing license and product delivery system. The unauthorized access, which began in July 2015, was discovered by Synopsys in October 2015.”
The fact that the company needs to make this announcement is indicative of a new attitude towards an old problem: Software companies who lose their products to theft and piracy no longer want to just buck up and get past it, particularly in EDA. Instead, they want tools and strategies to go after their adversaries. The newly launched startup SmartFlow Compliance Solutions, just announced last week, is planning to offer such tools.
Launched by Ted Miracco – one of the founders of EDA vendor AWR Corp. – SmartFlow is based on his experience dealing with pirated AWR product software, including tracking down and forcing restitution from companies who were proven culpable. In a phone call last week discussing his new company, Miracco said pirated software is more than just an occasional nuisance, it’s resulting in billions of dollars in lost revenue to the companies whose products are being used without licenses.
More profound than lost profits, however, is the ’tilting’ of the playing field. When companies who use pirated software to design chips or systems are able to undercut their competition by underpaying for the tools they need, or by not paying at all, the competition is hobbled.
In response, SmartFlow has engineered a complex set of tools and protocols that will allow companies to unearth pirated instantiations of their software across a variety of customer profiles. To begin their effort to build those tools, Miracco and his team looked closely at software non-compliance around the globe, parsed the different types of pirates and examined their principal strategies.
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Tags: AWR Corp., Cadence, Chris Luijten, EDA Consortium, Flexera, ITCA, L:ucent, Mentor Graphics, Mercedes Benz, Microsoft, Motorola, National Instruments, Nortel, SafeNet, SmartFlow Compliance Solutions, Software Piracy, Synopsys, Ted Miracco
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Wednesday, September 9th, 2015
ARM must be doing something right when among the eight corporate sponsors for their upcoming Silicon Valley users conference in November, the top three companies in EDA are listed as Diamond or Platinum.
Cadence is Diamond, undoubtedly, because company President & CEO Lip-Bu Tan is co-chair of EDAC, and ARM CEO Simon Segars is on the EDAC Board. But why would Mentor and Synposys spend good money being Platinum sponsors of ARM’s show when they could put that particular chunk of disposable income into their own user conferences, or even DAC? Particularly since Mentor and Synopsys sell IP, as does Cadence, so in some ways the three EDA companies may actually be competing with ARM.
There are three possible answers: A) Mentor, Synopsys, and Cadence serve as channels for ARM products. B) Mentor, Synopsys, and Cadence want to see, and be seen by, ARM’s enormous worldwide customer base. C) ARM has the winning hand in today’s semiconductor supply chain, so either the Big Three in EDA pony up to help sponsor ARM TechCon, or the UK-based IP behemoth won’t cooperate in the EDA world; they won’t offer pointers or tool-development advice for the third-party design software that EDA vendors sell and ARM customers [might] buy.
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Tags: ARM, ARM TechCon 2015, Cadence, EDA Consortium, Jane Austin, Lip-Bu Tan, Mentor Graphics, Pride and Prejudice, Simon Segars, Synopsys
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Wednesday, August 12th, 2015
Autumn used to start in September, but now classes and conferences commence in August and vacation ends just that much sooner. Here’s a list of various events you should consider attending between now and the end of the year, with thanks to conference organizers for the associated descriptions.
Scanning the range of topics, it’s clear the combined IP and EDA industries have an increasingly broad range of interests: IoT, autos, wearables, software security, verifying/integrating IP, power, device physics, memory, embedded processors and software, sensors, MEMS, a range of standards, networking, both the professional and technical kinds, and “synergistic collaborative design” both up in the cloud and down below on solid ground.
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Tags: 3D ASIP, Aart de Geus, ARC Processor Summit 2015, ARM, ARM TechCon 2015, Autonomous Cars 2015, Cadence, CDNLive, Connect Security World, DVCon Europe, DVCon India, GlobalFoundries, ICCAD 2015, IEDM 2015, Intel Developer Forum, MemCon 2015, Mentor Graphics, Mentor Graphics Forum, PCB West 2015, Si2Con, SMIC, Synopsys, TSMC, TSMC 2015 OIP Ecosystem Forum, Wally Rhines, Wearable Technology Conference
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Wednesday, April 1st, 2015
Early Monday morning, Synopsys announced several new bits have been added to their impressive bucket of IP blocks, a new family of DesignWare processors targeted at vision applications. With an honorable pedigree – descent from the ARC technology that came to Synopsys via the 2010 acquisition of Virage Logic – the processors announced on March 30th are designed to be embedded in SoCs, specifically to meet a growing need to digitally “distinguish smiles from frowns, faces from cars, baby carriages from trees or dogs, and even sky from ground.”
These needs were articulated in a March 26th phone call with Synopsys Senior Manager of Product Marketing Mike Thompson, who enthusiastically explained, “The vision market will grow dramatically over the next several years. The next 10-to-15 years will be seen as a paradigm-shift period in how we interact with technology.”
That’s why he’s delighted Synopsys will surpass other players in driving that shift: “There are already a few vision processors available [on the market], and they are largely programmable. We took a slightly different approach, however, with the new DesignWare EV Processors we’ve developed.
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Tags: ARC, ARC MetaWare Development Toolkit, ARM, Convolutional Neural Network, DesignWare, DesignWare EV Processors, Google, John Koeter, Mike Thompson, NEST, OpenCV, OpenVX, Synopsys, Virage Logic
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Tuesday, March 24th, 2015
We’re only gifted with so many hours of life here on earth, so why would anyone waste them listening to the same lengthy keynote twice in one month? That was the thought that raced through my mind when Synopsys’ Aart de Geus stepped up onto the stage in front of 500+ SNUG attendees at the Santa Clara Convention Center yesterday morning and clicked on his title foil.
“Shift Left,” it said.
“Oh no,” I said. For pity’s sake, this was the exact same talk co-CEO de Geus offered up less than three weeks ago on March 3rd at DVCon in San Jose. I looked around for the nearest exit.
Then, cooler heads prevailed. Mine.
Wait a minute, I said. Three weeks ago I sat in the back of a ballroom at the DoubleTree, listening over the heads of 350 people at DVCon, and typed everything the good doctor said into my tablet, verbatim. I’ve already done the heavy lifting here, I thought. I’ve got his script on my tablet, I’ve seen the slides, and I’ve heard the jokes.
Does Synopsys believe an entirely different audience attends DVCon than that which attends SNUG? Why else would they present the exact same talk at the two venues? Perhaps no one at SNUG actually does verification? Why not compare the SNUG talk to the one at DVCon?
So, with that much entertainment guaranteed I sat back and enjoyed the show.
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Tags: '66 Toronado, Aart de Geus, ARM, Chronologic, DVCon, EVE, finFET, Hardi, IoT, Legos, SNUG Silicon Valley, Springsoft, Synopsys, Synplicity
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Wednesday, January 28th, 2015
DVCon is coming up in early March in San Jose and if you’re into IP, you should be there. That was the surprising take-away I stumbled upon this week while interviewing DVCon General Chair Yatin Trivedi and Technical Program Chair Ambar Sarkar. As many of you know, Yatin is Director of Standards and Interoperability Programs at Synopsys and Ambar is Chief Verification Technologist at Paradigm Works, both men throwing long shadows in the deeply technical world of design and verification.
Our interview was taped on the sound stage in the glam new Synopsys building on Middlefield in Mountain View. Yatin works in the just-opened building, but Ambar flew in from his offices in Andover, Massachusetts, for our chat and was lucky enough to get out of Boston before Juno blew in and shut down all flights out of New England.
The three of us sat on director chairs on Monday morning and chatted on film for well over 30 minutes. Pretty darn fun, but also pretty darn informative. Who knew that Yatin and Ambar were so interested in IP, and we’re not just talking here about Verification IP. When I mentioned I’d seen that IP was one of the topic areas set to be showcased at the upcoming DVCon in March, Yatin launched into an enthusiastic endorsement of all things IP.
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Tags: Aart de Geus, Ambar Sarkar, Design Re-Use, DVCon, Paradigm Works, Steve Chappel, Synopsys, Yatin Trivedi
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Thursday, October 30th, 2014
This week Synopsys added even more fire-power to the arsenal that makes them one of the biggest IP vendors in the world. This time it’s USB 3.1, which the company says consists of a …
“DesignWare USB 3.1 Device Controller, an IP Virtual Development Kit and verification IP to accelerate the development of high-performance storage, digital office and mobile SoC applications. [The new product] supports 10 Gbps data transfer rates, power-down capabilities and compatibility with existing USB 3.0 software stacks and device protocols. Based on the DesignWare USB 3.0 Controller IP architecture, which has shipped in more than 100 million SoCs, the DesignWare USB 3.1 Device Controller IP enables designers to integrate USB 3.1 functionality with significantly less risk and faster time-to-market.”
As always, Synopsys delivers in a big way, which is why interviewing their people is always so much fun. These guys enjoy their work and know they’re on top, and not necessarily in that order. My phone call around the USB 3.1 announcement was with Eric Huang, Senior Product Marketing Manager for USB Digital IP at Synopsys, and was lively from start to finish.
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Tags: DesignWare USB 3.1, Eric Huang, Synopsys, USB 3.1
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Thursday, October 2nd, 2014
This blog requires a long, tall cup of coffee: Go get one, put your feet up, and plow on through. ARM TechCon 2014 took place this week at the Santa Clara Convention Center, and as an indication of what the industry feels is important right now, the following is a complex snapshot of press releases issued by various TechCon exhibitors highlighting their progress in the days leading up to and including the show. Listed first are the three main ARM press releases, then the other exhibitors are showcased.
By the way, the answer to what the industry thinks is important today? If the following is any indication, it’s IoT all the way down, with a dollop of FinFET and low-power thrown in for good measure. And if you don’t know IoT means Internet of Things, you haven’t been listening – particularly as Freescale says in their Press Release: “Analyst research firm Gartner estimates that the IoT will include 26 billion units installed by 2020, and by that time, IoT product and service suppliers will generate incremental revenue exceeding $300 billion, mostly in services.”
Another possible conclusion from the following: If you’re still holding out hope the Design Automation Conference is anchor tenant of the conference year, you should let that go. The amount of news these companies are releasing around ARM TechCon far out weighs what they’re releasing around DAC.
** ARM announced on October 1st “two new physical IP implementation solutions for its silicon partners to help simplify the path to implementation for their FinFET physical designs. ARM Artisan Power Grid Architect will reduce overall design time by creating optimal SoC power grid layouts, while ARM Artisan Signoff Architect increases accuracy and precision in managing on-chip variation over existing methodologies. These new physical IP implementation solutions strengthen the commitment from ARM to enable delivery of real silicon with the speed consumers are demanding.”
** ARM announced on October 1st, mbed OS, a free operating system for ARM Cortex-M processor based devices that consolidates the fundamental building blocks of the IoT in one integrated set of software components; mbed Device Server, a licensable software product that provides the required server-side technologies to connect and manage devices in a secure way, that also provides a bridge between the protocols designed for use on IoT devices and the APIs that are used by web developers; and mbed.org, the focus point for a community of more than 70,000 developers around mbed. The website provides a comprehensive database of hardware development kits, a repository for reusable software components, reference applications, documentation and web-based development tools.
** ARM and TSMC announced on October 2nd a new multi-year agreement that will deliver up ARMv8-A processor IP optimized for TSMC 10FinFET process technology. Per the Press Release: “Because of the success in scaling from 20SoC to 16FinFET, ARM and TSMC have decided to collaborate again for 10FinFET. This early path-finding work will provide valuable learning to enable physical design IP and methodologies in support of customers to tape-out 10FinFET designs as early as Q4 2015.”
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Tags: Acacia Communications, Airbus Defence and Space, Aldec, Altium Ltd., AMD, ANSYS, AppliedMicro, ARicent, ARM, ARM TechCon 2014, Arteris, ASSET InterTech, Atmel, Avago Technologies, Aviva Energy Corp., Cadence, Carbon Design Systems, Cavium, Cisco, Codasip, Doulos, Esterel, Express Logic, FreeBSD Foundation, Freescale, Gartner, GlobalFoundries, Green Hills Software, HP, IAR Systems, Intel, Internet of Things, IPSO Alliance, Lauterbach, LogMeIn, Mentor Graphics, Micrium, MontaVista Software, Mouser Electronics, Open-Silicon, P&E Microcomputer Systems, Rambus, Real Intent, Renesas Electronics, S2C, Samsung Electronics, SatixFy Ltd., SeeControl, SEGGER, Si2, SOMNIUM Technologies, Sonics, Spansion, STMicro, Synopsys, SYSGO, Teledyne LeCroy, TI, Toradex, TSMC, Undo Software, Uniquify, VanGogh Imaging, Vector Software, Wind River, Xilinx, XMOS, Zebra Technologies, Zuse Institute Berlin
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Monday, July 28th, 2014
There are three kinds of written word in the world today: books, newspapers/magazines, and all of the rest of it which now lives on the shifting sands of an ever-evolving electronic substrate. Even today, however, even as those ‘effervescent electrons’ garner more and more readers, it’s books-on-paper that continue to hold the most caché, the most gravitas-laden sense of permanence, and the most awe-inspring-for-the-ages kind of wow factor: Really? You wrote a book? Wow!
Hence, when a 220-page book-on-paper called Fabless: The Transformation of the Semiconductor Industry was made available to the EDA community at the 51st annual Design Automation Conference this past month in San Francisco, it was worth noting for several reasons: For the gravitas of the offering; For the permanence of the tome; And for the price, which thanks to eSilicon Corp. was free to all for the taking.
Written by SemiWiki.com gurus Daniel Nenni and Paul McLellan, this Fabulous Fabless book-on-paper was handed out during a buzzy networking event on the spacious East Side of Moscone Center early one evening during the week of DAC in June. At that noisy, ebullient reception, the libations were flowing liberally and so was the printed word.
Anyone milling about in the crowd quickly became the proud owner of Nenni/McLellan’s cheery, well-written history of the world – that special world consisting of everything termed “technology” since 1947 – and could even get signed copies, if they were able to elbow their way across the room to where the authors were perched side-by-side at a table with the express purpose of applying ink-to-paper on the front piece of their book.
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Tags: Altera, AMD, Apple, ARM, Arteris, Atrenta, C&T, Cadence, Calypto, CEVA, Chartered, Cliosoft, Coventer, Daniel Nenni, Docea, eSilicon, Fabless Semiconductor, GlobalFoundries, GSA, Imagination Technologies, Intel, Jasper, Mentor, Paul McLellan, SemiWiki.com, Sidense, Silvaco, Solido, Sonics, Synopsys, Tanner, TSMC, UMC, VLSI Technology, Xilinx
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Wednesday, June 4th, 2014
This week, in the early hours just prior to the opening of DAC, Synopsys announced a new initiative to reshape the world of IP. It’s called the IP Accelerated initiative, but it might as well as be called IP360. Just as Cadence’s EDA360 initiative was meant to reshape the design tool flow in the image of Cadence, Synopsys’ IP360 is meant to reshape the IP use and integration flow in the image of Synopsys.
And where EDA360 had three parts: System, SoC, and Silicon Realization, so IP360 has three parts: IP Prototyping, Architecting, and Integration. More specifically, the IP Accelerated initiative includes new IP prototyping kits with reference designs for IP preloaded into a HAPS-DX prototyping system, software development kits with processor subsystem reference designs and configurable models of DesignWare IP, and customized IP subsystems to augment Synopsys’ IP portfolio.
In other words, it’s all about “one-stop shopping,” per my September 30th conversation with Synopsys’ John Koeter, VP of Marketing for IP & Prototyping. “Synopsys has a broad portfolio of high-quality IP,” he said, and that combined with “our development kits for prototyping and software developmental” means that if you know how to reach Synopsys, you’re set and ready to go.
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Tags: Cadence, EDA360, IP Accelerated initiative, IP360, John Koeter, Synopsys
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