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Peggy Aycinena
Peggy Aycinena
Peggy Aycinena is a contributing editor for EDACafe.Com

DVCon: IP now part of the calculus

January 28th, 2015 by Peggy Aycinena

DVCon is coming up in early March in San Jose and if you’re into IP, you should be there. That was the surprising take-away I stumbled upon this week while interviewing DVCon General Chair Yatin Trivedi and Technical Program Chair Ambar Sarkar. As many of you know, Yatin is Director of Standards and Interoperability Programs at Synopsys and Ambar is Chief Verification Technologist at Paradigm Works, both men throwing long shadows in the deeply technical world of design and verification.

Our interview was taped on the sound stage in the glam new Synopsys building on Middlefield in Mountain View. Yatin works in the just-opened building, but Ambar flew in from his offices in Andover, Massachusetts, for our chat and was lucky enough to get out of Boston before Juno blew in and shut down all flights out of New England.

The three of us sat on director chairs on Monday morning and chatted on film for well over 30 minutes. Pretty darn fun, but also pretty darn informative. Who knew that Yatin and Ambar were so interested in IP, and we’re not just talking here about Verification IP. When I mentioned I’d seen that IP was one of the topic areas set to be showcased at the upcoming DVCon in March, Yatin launched into an enthusiastic endorsement of all things IP.

The gist of his soliloquy being that choosing and integrating IP is the only way we’ve accomplished all we’ve accomplished in the last number of years in the semiconductor industry, and the only way we will continue to achieve design miracles going forward. Ambar was equally enthusiastic and said many of the members of the Technical Program Committee at DVCon understand how the use of IP massively impacts many issues related to verification.

So, there you go. Clearly the authorities running DVCon appreciate the role of IP and are happy to confirm its importance to the folks who attend the conference. Nonetheless, there’s a catch.

After the Monday morning interview with Yatin and Ambar, I revisited the DVCon website and explored the various sessions and subjects set to be discussed therein. There’s lots of interest that will be under discussion at the DoubleTree Hotel in San Jose this year from March 2nd to 5th, just very little of it is specifically IP-related per se. Except for two sessions.

One is a company-sponsored tutorial offered by Synopsys’ Steve Chappel from 8:30 to Noon on Thursday, March 5th. The topic: Applying Re-Use Principles with an Open Debug Environment to Shrink SoC Schedules and Budgets. This is unambiguously a discussion of everything IP; that’s what “Re-Use” is all about.

And the other session? It’s the Tuesday afternoon keynote, also offered up by a Synopsys guy, Aart de Geus himself. The company’s co-CEO will be talking about “Smart Design from Silicon to Software” starting at 1:30 pm on Tuesday, March 3rd. The blurb on the DVCon website describing the keynote says: “The challenge for IC designers to keep pace has never been greater. The good news is that we’re up for it!”

Of course, by “we”, surely Dr. de Geus means Synopsys, one of the largest IP vendors in the world. Obviously, “smart design” begins and ends with the careful selection and integration of IP. Nobody’s designing anything from scratch any more. We all know that’s the case, and we also all know it’s one of the reasons Synopsys has grown to be as big and powerful as it is.

Clearly there’s lots more to talk about related to DVCon than the percentage of air time that will be devoted to IP. That will be obvious when the interview taped this week is posted live on the DVCon website, but meanwhile the sentiment still stands.

DVCon is coming up in early March in San Jose and if you’re into IP, you should be there. You can register here.


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One Response to “DVCon: IP now part of the calculus”

  1. Brenda says:

    Staffing by acquisition, or acihqre’ as someone recently coined on Techcrunch, is pretty common in the Web 2.0 industry but not unheard of in electronics or EDA. But this deal for product plus team is quite sizable, probably even if you compare it with the Model Technologies acquisition by Mentor Graphics over 15 years ago, or AccelChip by Xilinx over five (?) years ago.

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