Archive for the ‘Uncategorized’ Category
Thursday, May 9th, 2013
There’s a guy working away in Bangalore today who would like to change your ideas about what you pay for EDA tools. His name is Kanai Ghosh and his tool suite is called edautils, as in EDA Utilities. I spoke with Kanai on Skype recently about his efforts.
He told me that after a number of years working in EDA and CAD tool development, he decided to design his own suite of tools. Now several years into that process, working nights and weekends in and around his day job, Kanai’s tools are available for free download on his website.
Per Kanai, edautils pays particular attention to problems associated with integrating IP into larger SoC projects – a critical problem, he says, because today’s design projects can include more than 250 pieces of IP. In addition, today’s SoC has “multiple power and voltage domains” which the designer has to deal with by changing the design on the fly as the design constraints evolve, the designer constantly making “tradeoffs between power/performance/area and the project budget.”
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Tags: edautils, IEEE 1685-2009 IP-XACT, Kanai Ghosh
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Tuesday, April 30th, 2013
Bill Martin, President/VP of Engineering at E-System Design, sent a thoughtful response to my April 25th blog regarding Accellera’s recently released Soft IP Tagging 1.0 standard. I appreciate the time he took to clarify the ongoing need for such a standard.
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I was part of VSIA when Kathy Werner was driving the IP tagging standards. I am happy this one from Accellera is now out [Soft IP Tagging 1.0] and the various users can determine how best to apply it. It is a large step forward, but only one of many required.
Unfortunately, the current system for IP tagging can be easily ‘hacked’ to disable any tracking. Simple text editing the source code and removing a few lines can completely remove the tag. But Accellera’s standard is a good first step to hone the standard; understanding how it works and does not work for various constituents.
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Tags: Accellera, Bill Martin, E-System Design, GSA, GSA Interest Group, GSA IP ROI Calculator, IPextreme, Kathy Warner, Soft IP Tagging 1.0 standard, VSIA, Warren Savage
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Thursday, April 25th, 2013
Here’s a rhetorical question regarding Accellera Systems Initiative’s newly announced Soft IP Tagging 1.0 Standard: Is this the holy grail of IP or simply way too much information?
The question seems a fair one given the description in Accellera’s April 15th Press Release: “Normally, control of a third-party IP source is lost once the block of IP is licensed, unlocked, or otherwise made available in clear code. IP Tagging 1.0 facilitates a data-driven method to tag a block of IP and track ‘where used’ for applications such as ownership, royalty calculations, and recognition. It also facilitates the implementation of version identification for applicable bug fixes and errata and allows tracking of other data.”
This last bit, the part where bug fixes can be applied, is clearly the stuff of holy grails. But that first bit – reversing the “normal” loss of control regarding the source of third-party IP after it’s licensed and unlocked – isn’t the stuff of TMI, too much information revealed about something that may be better off kept under wraps?
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Tags: Accellera, Soft IP Tagging 1.0 standard
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Thursday, April 11th, 2013
Years ago, an editor/mentor advised me never to cover legal battles between companies in this industry. He’d always say, “There’s no good to be had from covering this stuff. The story’s always so much more complicated than anybody every fesses up to, so just don’t go there.”
So, how about this? Shall we accentuate the positive and decentuate the negative? You think that’s stupid, naive, not gritty enough? Well, y’all know where to go if you want to accentuate the negative and decentuate the positive. Y’all know where to go if you want the rumors and innuendo.
If, however, you’d rather start off your week with something a bit more upbeat, stick around.
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Tags: AMD, Barracuda Networks, Cadence, Dana Reyes, Emerson Hsiao, Fairchild Semiconductor, Faraday, Fujitsu, Host Analytics, James Lindstrom, Kilopass, Linh Hong, MagnaChip Semiconductor, MAZ Brandenburg, Samsung, Shanghai Haier IC, Sidense, Tatsuya Yamazaki, Tom Schild, TSMC, ZMDI
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Thursday, April 4th, 2013
Despite grumbling to the contrary, even some that I myself put forth in a blog earlier this year, there will indeed be a daily dose of IP information doled out at DAC in Austin in June. If you’re interested in IP, DAC 2013 actually promises to be quite informative. You can arrange your schedule so as to attend a single significant session each day devoted to various aspects of IP with all of its promise and particulars.
Here’s your DAC planning guide …
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Tags: Arteris, Atrenta, Chris Rowen, DAC 2013, Dan Kochpatcharin, David Murray, Duolog Technologies, Frank Ferro, Freescale, Hans Bouwmeester, IPextreme, John Eaton, John Swanson, Jose Nunez, Kamlesh Kumar Pathak, Keith Odom, Laurent Moll, Magillem Design Services, McKenzie Mortensen, Michael Cizi, Mike Gianfagna, Nagendra Gulur, National Instruments, Open-Silicon, Ouabache Designworks, Sonics, Southwest Reuse, STMicro, Sylvain Duvilliard, Synopsys, Tensilica, TI, TSMC, Vasant Kumar Easwaran, Warren Savage
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Thursday, March 28th, 2013
The best part of attending a conference like SNUG is plunging into a room of hundreds of anonymous lunch munchers and striking up a conversation with a stranger. Over the course of the meal, you’ll learn a little bit about somebody’s career, their expertise, and their concerns.
This week’s networking lunch at the Santa Clara Convention Center was no different. I had a chance to converse for 30 minutes with a lunch companion at a table full of strangers. By the end of the meal, I had heard first-hand about a really big problem for small IP vendors attempting to succeed in the current market – they can’t. According to my lunch companion, it’s nigh-on impossible to compete against ARM.
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Tags: ARM, GlobalFoundries, SMIC, SNUG, TSMC, UMC
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Thursday, March 21st, 2013
If you thought about going to the Synopsys Users Group meeting next week in Silicon Valley, there’s at least one topic that would make it worth your time: This week ARM and Synopsys announced “optimized 28-nm Synopsys Reference Implementations for ARM Cortex-A15 MPCore and Cortex-A7 MPCore processor clusters, as well as the CoreLink CCI-400 cache-coherent interconnect.”
The reference implementations are currently available, and include “scripts, floorplan, constraints and documentation” – scripts that are built on Synopsys’ tool Reference Methodologies and are optimized for high-performance cores. Clearly attending SNUG would clarify what you need to know to use all of this, but first apparently you need to understand ARM’s big.LITTLE processing. Which is what?
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Tags: ARM, ARM big.LITTLE processing, SNUG, Synopsys, Synopsys Reference Implementations
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Tuesday, March 12th, 2013
As the trading day in New York draws to a close, it would appear that some analysts are correct; the market’s not too pleased about yesterday’s announcement that Cadence is acquiring Tensilica. Shares of CDNS are trading down well over 3% today. But you know, the market’s stupid. They understand zip zero nada about EDA or IP, and really why should they?
After all, EDA and IP providers make the black magic that they do look so easy. And, they’re constantly telling people that what they do isn’t rocket science. But it is! The EDA vendors make the tools that IP vendors use to create their products, and designers use to integrate said IP into the larger designs. It’s called an eco-system and it is rocket science.
It’s also on the level of brain surgery, quantum physics, and a bunch of other esoteric science and engineering disciplines that require a lot of education and and a lot of OJT, and even then is really hard to do. How many traders on Wall Street, or the analysts who track it all, really understand what EDA and/or IP are all about? Exactly!
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Tags: ARM, Cadence, CDNS, Chris Rowen, EDAC CEO Panel, Lip-Bu Tan, Simon Segars, Synopsys, Tensilica
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Thursday, February 28th, 2013
If you’re free on the evening of Thursday, March 14th, you should plan on attending EDAC’s annual CEO Forecast Panel. It promises to be full of executive content, albeit perhaps a bit light on forecast content, but oh well. That’s the nature of life in the Publicly Traded Fast Lane these days.
Along with the CEOs of Mentor Graphics, Cadence, Synopsys, and Nimbic, the president of ARM will also be on stage, Simon Segars. Segars is no stranger to public speaking. You can hear his recent ARM TechCon 2012 keynote here. But it’s not what Segars will say on stage at the DoubleTree Hotel in San Jose on March 14th that matters. It’s his body language, and you’ll only be able to read that if you’re in the room.
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Tags: Aart de Geus, ARM, Cadence, EDAC, EDAC CEO Panel, Lip-Bu Tan, Mentor Graphics, Nimbic, Raul Camposano, Rich Valera, Simon Segars, Synopsys, Wally Rhines
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Thursday, February 14th, 2013
After the euphoniously monikered IP provider, Uniquify, announced several weeks ago that the more whimsically monikered organization, Pixelworks, is using Uniquify’s DDR memory controller subsystem IP for multiple distinct processors that Pixelworks is, in turn, providing to TV makers who make 4Kx2K ultra high-def systems, one question still remained: How did Pixelworks know to use Uniquify’s offering?
According to a January 2013 article in IEEE Spectrum, knowing what IP to use in a project here in the 21st century is fairly easy knowledge to come by. I don’t know what planet the author of the op-ed piece, “Other People’s Knowledge”, lives on but it doesn’t seem to be the one that I hear about from the folks who make or buy third-party IP.
In fact, those people seem to indicate that knowing what IP to use in a particular project continues to be far more art than science. In particular, because until a system, or sub-system, is fully defined, modeled and simulated – let alone, manufactured and deployed in the field – one can never really know how a piece of IP is going to work in the environment into which it’s been placed.
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Tags: BarcoSilix, Cadence, DDR memory controller IP, Eureka Technology, IP, Synopsys, TI, Uniquify, Xilinx
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