Archive for the ‘Uncategorized’ Category
Thursday, April 13th, 2017
Something eerie and inexplicable happened on Thursday evening, April 6th. Out of nowhere, an intense storm swept through the Bay Area, unannounced and without warning. The skies darkened, the winds howled, severe rain pelted the crowded, suddenly dangerous freeways, and hundreds of thousands lost power.
Meanwhile, exactly in the midst of the most violent part of this mysterious storm, the CEOs of the four most important companies within the ESD Alliance sat on stools in front of an audience assembled at Synopsys and chatted about this, that, and the other. Seemingly oblivious to the profound violence unleashing itself just outside the windows, they acted as if nothing was amiss.
Everything in the industry – and the world – was in order: Wonderful, with the data pointing continuously up and to the right, and everywhere ample evidence for a bullish, optimistic, and excited outlook on the future of EDA and IP.
No matter that Nature was having its way out there in the darkness, that the U.S. had bombed Syria the hour before their discussion began, that the drumbeat for answers about entanglements with Russia was quickening, or difficult conversations with the President of the PRC were underway that very day in Florida – the CEOs of Synopsys, Cadence, Siemens/Mentor Graphics and SoftBank/ARM sat relaxed and easy, basking in the evident vitality of the EDA and IP industries, and allowing themselves to be shepherded through a congenial confab of confident chit-chat by Ed Sperling of Semiconductor Engineering fame.
That fact that the vagaries of Nature never came into the conversation was not surprising; the fact the Mr. Sperling refused all opportunities to bring what he termed as “politics” into the conversation was quite the opposite. Surprising, that is.
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Tags: Aart de Geus, ARM, Brexit, Cadence, Ed Sperling, ESD Alliance, H1-B visas, Lip-Bu Tan, Mentor Graphics, Semiconductor Engineering, Siemens, Simon Segars, SoftBank, Synopsys, Walden C. Rhines
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Thursday, March 16th, 2017
It takes skill and surgical precision to launch and maintain a tech startup, especially today and extra-especially in a market as competitive as IP. Nonetheless, Massachusetts-based Performance-IP seems to have accomplished that feat.
It’s true, this is not the first IP company co-founded by Performance-IP CTO Gregg Recupero. In the early 1990’s, he helped to found VAutomation which developed IP for system-level verification [and was acquired by ARC in 2000].
In our phone call this week, I asked Recupero how a small IP company today can compete with the behemoth IP providers.
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Tags: Cadence, Gregg Recupero, Performance-IP, Synopsys, VAutomation
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Thursday, March 9th, 2017
Not for the first time, it’s become obvious that designing a bathroom is very similar to designing a chip. The effort requires a confident sense of the end-product you’re trying to accomplish – and then a great deal of necessary tedium.
Because these days, bathrooms and chips incorporate a huge number of IP blocks and the process of tracking down the final candidates, reworking the design over and over to see how each candidate fits in, then making the final selection, confirming with each IP vendor that the price and availability of their particular block meets your design budget and schedule, then nailing down the finished design, actually ordering and paying for the IP that will go into the design, and crossing your fingers that nothing untowards has happened between the moment you made your final part/IP selection and the moment the vendor’s supposed to pony up the goods.
The process of creating a bathroom or chip design that includes a great deal of IP is really complex. It requires a lot of shopping, validating, purchasing, receiving and integrating IP into the design.
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Tags: chip design, IP integration
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Thursday, February 23rd, 2017
Oski Technology has added a new page to its playbook. Now it’s not just a services company, it’s an IP company as well. This week, the company announced it’s Formal Verification IP Library targeted at those companies using ARM’s AMBA interface protocols.
When we spoke on the phone about the announcement, I asked Oski VP of Applications Engineering Roger Sabbagh why now for this product release. He said: “I personally have been working in Formal since the year 2000, back when I joined 0-In, and over the years I’ve learned that formal adoption grows slowly.
“Yet although there has never been a knee in the curve, we have seen some important developments in the industry. Synopsys developed PC Formal and Cadence bought Jasper, both indicating that Formal is catching on slowly but surely.”
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Tags: 0-In Design, Cadence, DVCon 2017, Formal sign-off, Jasper Design Automation, Mentor Graphics, Oski Tehnology, Roger Sabbagh, Synopsys
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Thursday, February 16th, 2017
Millions of people are talking about when we will stop driving our cars, many thousands are working on it, and six among those thousands made an appearance Tuesday evening, February 7th, on a panel at IEEE’s International Solid State Circuits Conference in San Francisco.
Over the course of the hour, the six speakers outlined their different visions of the technical roadmap that must be pursued to achieve fully autonomous cars. Of the six speakers, however, only three actually attempted to answer the panel prompt and their answers were wildly disparate.
So when will we stop driving our cars? 1) It’s impossible to know. 2) Not until 2030. 3) We already are beginning to stop driving our cars.
The panel was moderated by a senior Intel engineer, heavily involved in the company’s newly organized business unit specifically focused on autonomous driving systems.
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Tags: Autonomous driving cars, Daimler, Denso International America, IEEE ISSCC, Infineon, Intel, Jurgen Dickmann, Markus Tremmel, NVIDIA, Patrick Leteinturier, Robert Bosch, Roger Berg, Sahin Kirtavit, Self-driving cars, Umberto Santoni
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Thursday, February 9th, 2017
This week, the ESD Alliance announced that Sonics CEO Grant Pierce has been elected chair of the organization’s Board of Directors. His election is unique in several ways: Pierce is the first CEO of an IP company to lead the Alliance; he replaces two co-chairs, Cadence CEO Lip-Bu Tan and PDF Solutions, John Kibarian; and he is only the second CEO of a non-publicly traded company to serve as Board Chair, the other being Jasper CEO Kathryn Kranen who took the reins in 2012.
When Pierce and I spoke by phone on Tuesday about his election, he noted the unique circumstances of his new leadership role: “When I joined the board several years ago, it was with the intention to add a new point of view to what was then the EDA Consortium, to help the organization reflect the emerging reality of what was happening in the marketplace with respect to IP companies.
“In some ways, the IP companies consider themselves to be a necessary evil. Every chip developed today involves some sort of third-party IP, so having a place on the Board of the ESD Alliance is essential.”
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Tags: Aart de Geus, Amit Gupta, ARM, Bob Smith, Cadence, Cadence Design Systems, Dean Drako, EDA Consortium, EDAC, ESD Alliance, ESDA, IC Manage, John Kibarian, Lanza techVentures, Lip-Bu Tan, Lucio Lanza, Mentor Graphics, PDF Solutions, Simon Segars, Solido Design Automation, Sonics, Synopsys, Wally Rhines
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Thursday, January 19th, 2017
At the ESD Alliance panel on the Cadence campus Wednesday night, it was Vista Ventures’ Jim Hogan who suggested the little open-source processor architecture called RISC-V will prove itself to be a plucky survivor when looming market realities hit 800-pound proprietary vendors like ARM and Intel. Hogan suggested RISC-V is positioned to survive that pending apocalypse just like “the mammals after the asteroid.”
Pretty dramatic stuff.
Hence it should not have been surprising, at the end of the 75-minute discussion on stage between Jim Hogan and Microsemi’s Ted Speers and SiFive’s Yunsup Lee, that I raised my hand and asked why Simon Segars was not in the room. After all, Simon Segars is both CEO of ARM and a key member of the Board of the Alliance that organized the Hogan-Speers-Lee program – a program where the emerging RISC-V movement was described as poised to upend the primacy of ARM etc.
Hogan responded to my question without answering: “Look, ARM is challenging by serving the low-cost processor market. License fees, royalty fees – that is what ARM wants for their low-power edge-based device. I think it was Simon, for example, who started talking to The Street about his economic strategy. It’s not really about what the best technology is, but about the economics. This is what gets the traction, and ARM will respond in an economic way.”
“Yes,” Ted Speers added, “and Intel and Imagination will also respond.”
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Tags: ARM, Dave Paterson, ESD Alliance, Imagination Technologies, Intel, Jim Hogan, John Hennessy, Linley Group, Microsemi, Olivier Bernard, Rick O'Connor, RISC-V, RISC-V Foundation, SiFive, Simon Segars, Stanford, Ted Speers, U.C. Berkeley, Vista Ventures, Yunsup Lee
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Thursday, January 5th, 2017
One of your New Year’s Resolutions should be to further understand the philosophy, technology, and implications of the RISC-V movement. And there will be no better way to follow through on that resolution than to attend the upcoming ESD Alliance discussion on the topic.
In a nod to the best in situational irony, the Alliance is hosting an evening event in Silicon Valley on January 18th specifically to discuss this open source processor architecture, which per some has the potential to turn ARM’s market dominance on its ear.
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Tags: ARM, BSD License, DAC, Dave Patterson, ESC Boston, ESD Alliance, Google, IoT Meetup, Jim Hogan, Krste Asanovic, MIT, Oracle, Rick O'Connor, RISC-V, RISC-V Foundation, SiFive, U.C. Berkeley, Yunsup Lee
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Wednesday, December 14th, 2016
Flex Logic announced some astonishing news this week – the completed design of a “high-performance IP core for TSMC 16FF+ and 16FFC, with performance for wide, single-stage logic around ~1GHz at worst case PVT conditions.”
In a phone call to discuss the announcement, Flex Logic CEO and Co-founder Geoff Tate was clearly ebullient: “Last August we were talking about TSMC’s 40-nanometer ULP, ultra low power, and now this week we’re talking about the first 16-nanometer finFET plus.
“This one, our EFLX 100, is like the one we announced at 40 nanometers – but at 16 nanometers it will run much faster!
“We’ve done extensive measurements [to confirm] for many applications that these cores will run at 1GHz or faster, even in worst-case temperature conditions.”
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Tags: EFLX-100 cores, embedded FPGA, Flex Logic, Geoff Tate, TSMC, TSMC 16FF+
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Wednesday, December 7th, 2016
If you’re a designer looking for a rare opportunity to shine, look no further. The folks at Erfurt-based X-FAB and Silicon Valley-based efabless hope to “further ingenuity” by extending a challenge to anyone in the world willing to accept it.
What they’re looking for are IP designs applicable to an ultra-low power voltage reference, and the companies are willing to make it worth your while.
If your design is one of the top three selected, you’ll receive a monetary award and your IP will be made available to a global customer base through both X-FAB’s IP web portal and efabless’ online marketplace.
Best of all – you’ll hold onto all rights for your submission.
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Tags: eFabless, IP Design Challenge, Mohamed Kassem, Ulrich Bretthauer, X-Fab
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