IP Showcase 
Peggy Aycinena
Peggy Aycinena is a contributing editor for EDACafe.Com Freescale’s Nunez: Get it in writing before integrating External IPJune 12th, 2013 by Peggy Aycinena
Freescale IP Design Manager Jose Nunez presented a tutorial on Tuesday, June 4th, at the Design Automation Conference in Austin entitled “Challenges of Integrating External IP”. Through a show of hands, he found the majority of his audience were IP users and therefore knew his comments would be of more than passing interest. Nunez first noted there are even challenges in reusing internally-generated IP – big companies often have multiple groups, each with different ways and methodologies for designing IP blocks. He said, however, his talk would focus on licensing third-party IP – standard IP such as PCI Express and USB, which would add no value to Freescale if developed internally, as well as other types of IP, which if developed internally might exceed a need-by date. In such cases, he said, licensing third-party IP almost always proves cheaper in the long run, but it has to be done with care! Nunez cited common misconceptions: 1) When companies use widely-available third-party IP from known providers, it means those blocks come with fewer bugs. 2) If everybody’s using third-party IP, it can’t be that hard to integrate it into a project. 3) Third-party IP always delivers best-in-class features, maturity, power and speed. Having set the stage, he then listed some straightforward guidelines for interfacing with IP vendors, and using their products. Read the rest of Freescale’s Nunez: Get it in writing before integrating External IP DAC 2013: IP news in advance of AustinMay 30th, 2013 by Peggy Aycinena
** IPextreme announced it will collaborate with its Constellations program members and other key players in the semiconductor IP ecosystem to host the Stars of IP Party on June 4th, an event coinciding with DAC 2013 in Austin, Texas. The company says Stars of IP celebrates “all things semiconductor IP” and seeks to build relationships among IP provider companies and customers, thereby strengthening the ecosystem. Co-hosting with IPextreme are Atrenta, CAST, Certus Semiconductor, Recore Systems, Sonics, Synopsys, and True Circuits. Kanai Ghosh: A singular effort that changes the conversationMay 9th, 2013 by Peggy Aycinena
There’s a guy working away in Bangalore today who would like to change your ideas about what you pay for EDA tools. His name is Kanai Ghosh and his tool suite is called edautils, as in EDA Utilities. I spoke with Kanai on Skype recently about his efforts. He told me that after a number of years working in EDA and CAD tool development, he decided to design his own suite of tools. Now several years into that process, working nights and weekends in and around his day job, Kanai’s tools are available for free download on his website. Per Kanai, edautils pays particular attention to problems associated with integrating IP into larger SoC projects – a critical problem, he says, because today’s design projects can include more than 250 pieces of IP. In addition, today’s SoC has “multiple power and voltage domains” which the designer has to deal with by changing the design on the fly as the design constraints evolve, the designer constantly making “tradeoffs between power/performance/area and the project budget.” Read the rest of Kanai Ghosh: A singular effort that changes the conversation Bill Martin: clarifying Accellera’s IP Tagging 1.0 StandardApril 30th, 2013 by Peggy Aycinena
Bill Martin, President/VP of Engineering at E-System Design, sent a thoughtful response to my April 25th blog regarding Accellera’s recently released Soft IP Tagging 1.0 standard. I appreciate the time he took to clarify the ongoing need for such a standard. ****************** I was part of VSIA when Kathy Werner was driving the IP tagging standards. I am happy this one from Accellera is now out [Soft IP Tagging 1.0] and the various users can determine how best to apply it. It is a large step forward, but only one of many required. Unfortunately, the current system for IP tagging can be easily ‘hacked’ to disable any tracking. Simple text editing the source code and removing a few lines can completely remove the tag. But Accellera’s standard is a good first step to hone the standard; understanding how it works and does not work for various constituents. Read the rest of Bill Martin: clarifying Accellera’s IP Tagging 1.0 Standard IP Tagging 1.0 standard: Holy Grail or TMI?April 25th, 2013 by Peggy Aycinena
Here’s a rhetorical question regarding Accellera Systems Initiative’s newly announced Soft IP Tagging 1.0 Standard: Is this the holy grail of IP or simply way too much information? The question seems a fair one given the description in Accellera’s April 15th Press Release: “Normally, control of a third-party IP source is lost once the block of IP is licensed, unlocked, or otherwise made available in clear code. IP Tagging 1.0 facilitates a data-driven method to tag a block of IP and track ‘where used’ for applications such as ownership, royalty calculations, and recognition. It also facilitates the implementation of version identification for applicable bug fixes and errata and allows tracking of other data.” This last bit, the part where bug fixes can be applied, is clearly the stuff of holy grails. But that first bit – reversing the “normal” loss of control regarding the source of third-party IP after it’s licensed and unlocked – isn’t the stuff of TMI, too much information revealed about something that may be better off kept under wraps? Read the rest of IP Tagging 1.0 standard: Holy Grail or TMI? IP @ DAC: a session a day keeps the doctor awayApril 4th, 2013 by Peggy Aycinena
Despite grumbling to the contrary, even some that I myself put forth in a blog earlier this year, there will indeed be a daily dose of IP information doled out at DAC in Austin in June. If you’re interested in IP, DAC 2013 actually promises to be quite informative. You can arrange your schedule so as to attend a single significant session each day devoted to various aspects of IP with all of its promise and particulars. Here’s your DAC planning guide … Read the rest of IP @ DAC: a session a day keeps the doctor away SNUG: Lunch with a proper strangerMarch 28th, 2013 by Peggy Aycinena
The best part of attending a conference like SNUG is plunging into a room of hundreds of anonymous lunch munchers and striking up a conversation with a stranger. Over the course of the meal, you’ll learn a little bit about somebody’s career, their expertise, and their concerns. This week’s networking lunch at the Santa Clara Convention Center was no different. I had a chance to converse for 30 minutes with a lunch companion at a table full of strangers. By the end of the meal, I had heard first-hand about a really big problem for small IP vendors attempting to succeed in the current market – they can’t. According to my lunch companion, it’s nigh-on impossible to compete against ARM. ARM & SNPS: implementing big.LITTLEMarch 21st, 2013 by Peggy Aycinena
If you thought about going to the Synopsys Users Group meeting next week in Silicon Valley, there’s at least one topic that would make it worth your time: This week ARM and Synopsys announced “optimized 28-nm Synopsys Reference Implementations for ARM Cortex-A15 MPCore and Cortex-A7 MPCore processor clusters, as well as the CoreLink CCI-400 cache-coherent interconnect.” The reference implementations are currently available, and include “scripts, floorplan, constraints and documentation” – scripts that are built on Synopsys’ tool Reference Methodologies and are optimized for high-performance cores. Clearly attending SNUG would clarify what you need to know to use all of this, but first apparently you need to understand ARM’s big.LITTLE processing. Which is what? M&A: CDNS + Tensilica = win/winMarch 12th, 2013 by Peggy Aycinena
As the trading day in New York draws to a close, it would appear that some analysts are correct; the market’s not too pleased about yesterday’s announcement that Cadence is acquiring Tensilica. Shares of CDNS are trading down well over 3% today. But you know, the market’s stupid. They understand zip zero nada about EDA or IP, and really why should they? After all, EDA and IP providers make the black magic that they do look so easy. And, they’re constantly telling people that what they do isn’t rocket science. But it is! The EDA vendors make the tools that IP vendors use to create their products, and designers use to integrate said IP into the larger designs. It’s called an eco-system and it is rocket science. It’s also on the level of brain surgery, quantum physics, and a bunch of other esoteric science and engineering disciplines that require a lot of education and and a lot of OJT, and even then is really hard to do. How many traders on Wall Street, or the analysts who track it all, really understand what EDA and/or IP are all about? Exactly! |
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