Warning: Undefined array key "meta_description" in /www/www10/htdocs/blogs/wp-content/themes/ibs_default/header.php on line 92
EDACafe: IP Showcase
Open side-bar Menu
 IP Showcase
Peggy Aycinena
Peggy Aycinena
Peggy Aycinena is a contributing editor for EDACafe.Com

Standards: the Elephant jumped over the Moon

 
October 24th, 2013 by Peggy Aycinena

Let’s just be bold and identify the elephant in the room: If IP providers and/or EDA tool vendors really wanted standards that were ubiquitous, complete, and effective, they would have implemented them years ago. But they don’t. Similarly, if IP users and/or EDA tool users really wanted standards that were universal, robust and truly useful, they would have demanded them years ago. But they don’t.

The truth is that IP providers are happiest when they’re insisting that their proprietary interface is the best, and ergo should be the de-facto industry standard. And it goes without saying that whatever they’re providing inside of their black box is, of course, best-in-class. Certainly no standards are ever going to be inserted in there, and for good reason! Full stop.

Meanwhile, IP users clearly consider the problem of integrating IP into their projects as an accepted, even advantageous cost of doing business here in the 21st century. The way they integrate third-party IP into their systems is tantamount to a secret sauce – one that’s cooked up in NDA arrangements between the user and the provider – and not something any IP user wants to make public by way of standards, or any other device, for fear their hard work learning/mastering the integration of IP, if revealed, might give a leg-up to the competition.

Read the rest of Standards: the Elephant jumped over the Moon

IP Sampler: Self-evident truths

 
October 17th, 2013 by Peggy Aycinena

A brief sampler of recent announcements on the IP front reveal distinct themes in the marketplace. IP development and integration require a viable ecosystem of suppliers and tool vendors; automotive, audio and mobile apps continue to be important targets for IP developers whose customers seek better safety, longer battery life, and truer sound (particularly for sporting events and concerts of aging rockers); IP interfaces remain crucial; and platform-based design totally depends on further enhancements in IP technologies.

Additionally, acquisitions definitely pan out for the companies smart enough to snap up the good ones: Synopsys/ARC, Cadence/Tensilica, and Imagination/MIPS.

Read the rest of IP Sampler: Self-evident truths

OneSpin’s Cloud vision: Knock, knock, knocking at heaven’s door

 
October 2nd, 2013 by Peggy Aycinena

If heaven is in the Cloud, OneSpin is knocking at the door, because last week the company announced its Cloud Computing System moved from beta to full-on availability on Amazon Web Services (AWS) Marketplace. There it “provides secure and fully automated solutions for advanced formal verification, offering the functionality provided by OneSpin 360 DV-Inspect and 360 DV-Verify.”

This news is interesting if you think it’s a rarity for an EDA company to brag on their Cloud capability, the received wisdom being that neither EDA vendors nor EDA customers want to conduct their technical business outside of their own firewall. Given the less-than-remarkable traction that Cloud-based anything has had in the EDA/IP ecosystem, it was great to have a chance to speak to OneSpin’s Dave Kelf this week regarding his company’s news.

I asked Kelf why the Cloud’s been slow to catch on in the industry. He said, “Basically, the Cloud has been tried by a whole bunch of EDA companies with varying degrees of success. Even when I was at Cadence, we played with the Cloud but didn’t get anywhere at all. The reason is that most companies are concerned about their IP and don’t want to let it out of their office. They’re nervous about putting it out on the Cloud.

Read the rest of OneSpin’s Cloud vision: Knock, knock, knocking at heaven’s door

EDAC Seminar: EDA & Export Compliance

 
September 26th, 2013 by Peggy Aycinena

EDAC hosted an evening seminar last week that could have taught you everything your company needs to know to meet your Export Compliance requirements – an unbelievably labyrinthine set of rules, created and nurtured by various agencies of the U.S. Government, that are designed in part to prevent sensitive technical IP from falling into the hands of less-than-totally-friendly nation states.

If you weren’t there on September 18th, you were not alone. A surprisingly small number of people showed up for the seminar, although the speaker, Cadence Group Director for Export Compliance and Government Relations Larry Disenhof, is clearly a walking encyclopedia on this stuff, and although EDAC did a great job publicizing the event.

If you didn’t attend EDA & Export Compliance, it was probably for one of two reasons:  Your team already knows everything they need to know in order to meet their export obligations, or your team is oblivious to the fact that these requirements are not optional; they’re obligatory and failure to comply can precipitate fines of $250,000 and up, loss of export privileges, cancellation of pending M&A’s, and even jail time.

Read the rest of EDAC Seminar: EDA & Export Compliance

Tezzaron: You’ve got our attention now

 
August 29th, 2013 by Peggy Aycinena

Tezzaron Founder and CTO Bob Patti delivered a rousing keynote at the Silicon Valley Magma User Group meeting back in 2010, talking about his company’s 3D memory technology and how it offered a solution to the increased demands for on-chip capacity. I spoke to Patti following that speech, with details of the conversation posted here.

In the past 3 years, things have only gotten worse with respect to memory demands, so one might think Tezzaron’s solution is in even greater demand today. The problem, of course, is that Tezzaron Semiconductor is not the only company offering something that looks like ‘3D memory.’

In fact, 3 weeks ago at MemCon 2013 in Silicon Valley, I attended a keynote given by Micron Technology’s Mike Black singing the praises of his company’s Hybrid Memory Cube. Sitting in the audience, I tried to compare and contrast the Micron technology with what I believed to be the Tezzaron solution.

Happily, Tezzaron had a booth at MemCon, so it was possible to talk to somebody from the company about how they viewed Micron’s competing technology. Unfortunately, Tezzaron VP David Chapman was surrounded by a mob of interested people when I got to the booth, so I took his card and arranged to talk to him later about my many questions.

My number one question: Given the size of Micron and the ecosystem of partners they’ve assembled, the Hybrid Memory Cube Consortium, is Tezzaron winning the battle of technology superiority, but losing the war for market share?

Tezzaron’s Chapman was not offended by my question. Instead, he started by framing his answer with a description of current market needs and continued from there. The following is a transcript of his comments.

Read the rest of Tezzaron: You’ve got our attention now

SNPS Sensor Subsystem: far-reaching implications

 
August 15th, 2013 by Peggy Aycinena

Late last month, Synopsys announced another important addition to their portfolio, the DesignWare Sensor IP Subsystem. Per the company, “The new IP subsystem is optimized to process data from digital and analog sensors, offloading the host processor and enabling more efficient processing of the sensor data with ultra-low power.

“The hardware components [include] a power- and area-efficient DesignWare 32-bit ARC EM4 processor, digital peripherals such as I2C, SPI, ADC interface, and GPIO, and hardware accelerators for signal processing functions. The software components [include] a comprehensive library of digital signal functions utilized in higher-level applications such as analog and digital sensor fusion, and mathematical functions, filtering and interpolation. In addition, peripheral drivers ease integration of the I/O with the ARC EM processor.”

With announcements such as this, two questions come to mind: Why are companies like Synopsys still classified as EDA with some IP, and not IP with some EDA? And isn’t Synopsys setting itself up as competition for its customers by selling such a sophisticated chunk of IP?

I had a chance to speak by phone last week with Rich Collins, Marketing Manager for Synopsys’ IP Subsystems, who answered my second question with ease: “I don’t think so, because this [subsystem] is not a critical part of the SoC. Our customers are trying to achieve a higher order of functionality. It’s our value proposition that by using this subsystem, we save them months and months of design and verification effort. We help them get to market more quickly, we are not in competition with them.”

Read the rest of SNPS Sensor Subsystem: far-reaching implications

Future of IP: from Tensilica to IPextreme

 
August 1st, 2013 by Peggy Aycinena

Bill Martin, President/VP of Engineering at E-System Design, has sent another thoughtful response to a blog regarding IP, in particular my post last week about the astonishing increase in the valuation of ARMH over the last 5 years.

********************

Years ago, Chris Rowen had a clear vision where EDA and IP would start to merge, given the complexities of both. He knew both could have a large impact on the resources and risks associated with creating an SoC. His vision was so compelling, Chris resigned from a great group within Synopsys to form his start-up, Tensilica.

At the time, EDA/IP/Customization were all difficult problems to resolve. By building larger blocks that automatically reconfigured and combined other aspects (examples: SW compiler/debugger for code that could add/delete instructions and a verification suite that reconfigured themselves based customers’ usage), the solution Chris created at Tensilica addressed SIP/Embedded SW/VIP and EDA.

Quite an ambitious undertaking, but over time as his solution was honed and matured, the industry saw the end result – a few months ago the large acquisition of Tensilica by Cadence. In fact, the deal was part of a trend. Look at the various EDA and IP acquisitions since 2008, those exceeding $100 million:

Read the rest of Future of IP: from Tensilica to IPextreme

Money matters: It’s an IP, IP, IP, IP World

 
July 25th, 2013 by Peggy Aycinena

Fifty years ago, you would have known that it was a Mad, Mad, Mad, Mad World. Today, however, it’s an IP, IP, IP, IP World. Should you choose to cling to any skepticism about this state of affairs, here’s how to get over it.

Below you’ll find a very rough set of numbers [gleaned from Yahoo Financials] that look at the stock valuations of four companies that Play Large in the world of EDA and IP.  You’ll see posted there, a compare/contrast of the corporate performances of Mentor Graphics, Synopsys, Cadence, and ARM over the last 1 year, 2 years, and 5 years.

Remember back to the summer of 2008? The sky was falling, the world’s economy was  hell-bent on reaching the brink of cataclysmic collapse, and although Cadence was aggressively going after Mentor Graphics, the company was in truth only a handful of weeks away from a complete collapse of its own, the dismembering of the executive team in mid-October 2008.  Given the drama of that time, could we have predicted where we would be today?

Read the rest of Money matters: It’s an IP, IP, IP, IP World

5S: The Kaizen of SIP

 
July 18th, 2013 by Peggy Aycinena

We are all familiar with the 5S mantra for running a tightly choreographed manufacturing operation. It’s an intuitively pleasing and simplified set of rules for improving and maintaining physical plants, and can be targeted at everything from making cars to creating an effective commercial lab space. The ideas behind Sort, Straighten, Scrub, Standardize, and Sustain are closely linked to the writings of just-in-time efficiency expert Hiroyuki Hirano, and are also often associated with the term Kaizen.

Taking into consideration the admirable characteristics of Kaizen, is it possible to contemplate a 5S program for using semiconductor IP in a lean and efficient way? Although any number of S’s might fill the bill, let’s consider Seek, Sort, Satisfy, Stitch, and Sell as one such assembly of terms that could guide the IP user.

Read the rest of 5S: The Kaizen of SIP

Update: IP on the move

 
June 20th, 2013 by Peggy Aycinena

Despite their marked contributions to DAC in Austin, the folks in the IP world have not been resting on their laurels, but have continued to generate developments of both a technical and business nature.


**
Synopsys and OCZ Technology Group announced OCZ “achieved first-pass silicon success” in its newest NAND flash Vector SSD using Synopsys’ DesignWare DDR2/3-Lite PHY, Embedded Memories, STAR Memory System, and Professional Services.

The companies say the OCZ Vector SSD was designed “to deliver superior sustained performance through its new, high-performance Indilinx Barefoot 3 flash controller supporting the SATA-3 protocol. Synopsys’ design consultants worked closely with OCZ’s engineers throughout the implementation of their chip, delivering expertise and advanced methodologies in IP integration, physical design, and physical verification that enabled OCZ to complete their implementation in less than six months.”

Read the rest of Update: IP on the move




© 2024 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
TechJobsCafe - Technical Jobs and Resumes EDACafe - Electronic Design Automation GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise