Archive for May, 2016
Thursday, May 26th, 2016
There are clearly a lot of collateral distractions at the Design Automation Conference: Networking. Social Hours. Parties. Chotzkies. But the real fun at DAC comes from carving time out to attend technical sessions. This is year in Austin, the offerings are particularly rich.
On Sunday, June 5th, my two favorites are: The Workshop on Design Automation for Cyber-Physical Systems, and The Workshop on Computing in Heterogeneous, Autonomous ‘N’ Goal-Oriented Environments. Both of these all-day events feature experts from academia and industry, most speaking for at least 30 minutes. The topics will be very technical and the schedules allow for detailed presentations. Of course, this doesn’t mean the other workshops on Sunday don’t have great merit, but the two I have identified look to be particularly rich opportunities for learning.
Sunday evening, for the first time, there will also be a 2-hour panel focused on Career Perspectives in EDA, a discussion sponsored by CEDA. Although many will be obliged to attend networking dinners on Sunday evening, or will still be busy setting up booths for Monday morning’s Exhibit Hall opening, attending this Career Panel seems an opportunity not to be missed, particularly as it will be moderated by the supremely knowledgeable Bill Joyner from SRC. Admittedly, this is not a technical session, but the implications for the industry are profound. [File under the heading: ‘Concern for an Aging Industry’]
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Tags: 3D IC, Accellera, Bill Joyner, CEDA, Cyber-Physical Systems, DAC 2016, Design Automation Conference, Edward McCluskey, emulation, Heterogeneous Systems, IoT, Jason Cong, John Sanguinetti, Luca Carloni, Mark Horowitz, Nano-Scale Era, Post Silicon Diagnosis, Power Management, Simulation, UVM
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Thursday, May 19th, 2016
It’s a poorly kept secret that Bob Smith was brought in as Executive Director of EDAC last year to shake things up, to breathe new life into the sails of a somewhat becalmed organization. Well, in the category of be careful what you ask for, here’s how things have gone so far:
New companies have joined the consortium, the newest member of the Board of Directors is not a CEO, a plethora of monthly panels have engaged the industry in thought-provoking discussions about innovation vis-à-vis commercial enterprise, a marketing deal has been struck with Semico, and the whole friggin’ organization has been re-branded as the ESD Alliance to reflect an intent to get more IP guys, more Embedded guys, and more Yet-to-be-identified guys into the alliance than just the traditional anchor tenants from EDA.
But none of this comes close to the potential impact of the latest disruptive idea that ESDA is proposing: The founding of a brand new working group that could very well redefine the whole semiconductor supply chain: The ESD Alliance System Scaling Working Group.
Astonishing.
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Tags: Accellera, Bob Smith, EDAC, ESD Alliance, GSA, Herb Reiter, IEEE, Sematech, Semi, Semico, Si2, System Scaling Working Group
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Thursday, May 12th, 2016
IP will be well represented at DAC according to Adapt IP Michael “Mac” McNamara, and he should know. He’s helped build the IP Track at the show and is concerned that everyone understand the IP-related content in Austin this year will be deep and wide.
Mac and I spoke by phone recently. He’d read a blog a posted here in April expressing skepticism about IP coverage at DAC. Therein, I suggested the content set for Austin in June was inadequate, given the important role IP plays in chip design today.
A thoughtful McNamara wanted to respond to this critique; he wanted to evangelize for the quality of the content at DAC – particularly as he is Vice Chair of the conference this year and will be General Chair in 2017. [Cadence’s Chuck Alpert is General Chair here in 2016.]
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Tags: Adapt IP, Anne Cirkel, ARM, DAC 2016, Design Automation Conference, DesignCon, DVCon, ICCAD, IPextreme, Mentor Graphics, Michael McNamara, Synopsys, Warren Savage
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Thursday, May 5th, 2016
Warren Savage, CEO at IPextreme, is willing to address questions regarding IP content at DAC 2016, enthusiastic in fact. That’s not surprising, given that he serves on the IP Track Committee that reviews the content.
“I think the content’s very good this year,” Savage said in a recent phone call. “We’ve been working on the IP content at the DAC for 3 years, and continue to make progress. I would say the biggest thing [we struggle with] is insufficient time allocated for IP.
“In comparison to previous years, however, the IP and Design tracks have been merged and all put under the same track – something we recommended against, because design-related submissions generally are different from IP-related submissions.”
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Tags: DAC 2016, ESD Alliance, IPextreme, Warren Savage
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