Posts Tagged ‘Synopsys’
Thursday, July 5th, 2012
The SI landscape is a confusing one: What is the true value of a signal integrity analysis tool, and if you’re an EDA vendor, do you need to offer an in-house SI solution to be a true end-to-end provider?
Although Cadence has had a position in signal integrity with their OrCAD Signal Explorer [pre- and post-route topology exploration and transmission line analysis, conceptual, pre-design/schematic topology exploration and simulation, routed or unrouted board topology extraction and analysis] …
… this week Cadence announced it has acquired Silicon Valley-based Sigrity and will now incorporate Sigrity’s PowerSI [full-wave electrical analysis for IC packages and PCBs, identifies trace and via coupling, power/ground bounce, and design regions that are under or over voltage targets] and SystemSI [chip-to-chip signal integrity analysis, including parallel bus analysis and serial link analysis, frequency domain, time domain and statistical analysis] into Cadence’s flow.
This all sounds great as a strategy for beefing up Cadence’s SI offerings, but what does it do to Sigrity’s current set of partners: Apache [owned by Ansys], CST, Mentor Graphics, Synopsys’ HSPICE, TSMC, and Zuken?
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Tags: AJ Incorvaia, Ansoft, Ansys, Apache, Cadence, CST, HSPICE, HyperLynx SI, Lightning Verify, Mentor Graphics, OrCAD, PowerSi, SI, SIgnal Integrity, Sigrity, SiSoft, Synopsys, SystemSI, TSMC, Zoltan Cendes, Zuken
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Monday, June 4th, 2012
DAC started with a boom on Sunday night, June 3rd. EDAC reports that 900 people registered for the opening reception, and by the crush of people in Salon 7 in the basement of the San Francisco Marriott Hotel, it looked like everybody showed up. [Although perhaps not quite 900…]
Setting up my word processor on a cocktail table at the back of the crowd, I manged to see numerous thought leaders in EDA as they swam by, in and out of the stream of people that swirled throughout the wine, buzz & music-laden ballroom as EDAC’s Executive Director Bob Gardner’s Jazz Trio entertained up on stage.
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Tags: #49DAC, Bob Gardner, Chris Rowen, DAC, DAC 2012, DAC 2013, Design Automation Conference, EDAC, Jennifer Cermak, Jill Jacobs, Lee Woods, Mentor Graphics, MOD Marketing, MP Associates, OpenAccess, Ry Schwark, Si2, Steve Schulz, Synopsys, Tensilica, Wally Rhines
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Wednesday, May 16th, 2012
 On May 1st, Joe Costello was standing in his office at Orb Networks on the 6th floor of a building in downtown Oakland. When we started our phone call, he said, “I’m looking down on Broadway and there’s a massive march out there. It’s crazy — wish I could send you the video!”
It was, of course, the May Day Occupy Oakland march, which seemed just about right for this long-planned interview.
Twenty years ago, Joe Costello was CEO at Cadence; today he’s President & CEO at Orb Networks, a company that’s “cranking away at cool stuff in the media space.” Twenty years ago, Joe Costello was the epicenter of EDA; today he’s roiling things up elsewhere in the technology ecosystem.
So first we talked about Joe’s present and future, and then we got around to EDA’s present and future and What Would Joe Do if he was back in the epicenter today.
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Tags: Cadence, EDA, EDA investment, Joe Costello, Lucio Lanza, Mentor Graphics, Oasys Design Systems, Orb Networks, Synopsys
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Tuesday, May 8th, 2012
DAC looms!
 And never more so than on Tuesday — especially this year, June 5th, when you’re going to have to make some terrible decisions about what to miss, and what not to miss.
First there’s the opening session in the morning when a boatload of awards are handed out, followed by the 2012 keynote. The Exhibition Hall won’t open until these things wrap up, so other than company meetings or company special-product announcement breakfasts, you should be able to be in the main theater at Moscone from 8:30 to 10:00 am or so.
Of course, worst case scenario: The opening session at DAC is always video-taped, so you could watch it at a later date after it’s uploaded to the DAC website but that’s hardly ideal.
This year’s main address will be delivered by ARM’s Mike Muller, “comparing the original ARM design of 1985 to those of today’s latest microprocessors … how far design has come and what EDA has contributed to enabling … systems, hardware, operating systems, and applications.” Then Muller plans to talk about 2020, how to get there, and what it will be like when we do. Conclusion? This stuff’s better heard in person than tape delayed. Go to the opening session, and plan not to regret it.
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Tags: ACM, Applied Micro, ARM, Atrenta, Brian Fuller, Cadence, CEDA, Chevy Volt, Cisco, DAC, Design Automation Conference, IPL Alliance, Jim Hogan, Jim Solomon, LSI, Mark Horowitz, McKormick & Kuletos', Mike Muller, PMC-Sierra, Realtek, STMicro, Synopsys, Xilinx, Yervant Zorian
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Thursday, May 3rd, 2012
The Sophia Antipolis Microelectronics Forum takes place every fall in the ‘Silicon Valley’ of Southern France, Sophia Antipolis, 5 miles inland from the beautiful Mediterranean city of Antibes.
Sophia Antipolis is about 20 minutes from the International Airport at Nice, with offices for approximately 800 high-tech companies – included among them: ARM, Broadcom, Cadence, HP, IBM, Infineon, Intel, Mentor Graphics, Nvidia, STMicro, and Synopsys – housed in a range of buildings set among the rolling hills of the enclave. Within that forested place and 800 enterprises, almost 40,000 people are employeed. There are also two college campuses in Sophia Antipolis, as well as restaurants, a golf course, multiple hotels, and a tennis institute.
In other words, if you’ve never been to the Cote d’Azur, never been to Nice or Antibes, if you think you’d love vistas across the wide blue Mediterranean Sea, want to learn more about good food, wine, Picasso, Matisse, ancient Greeks, the French Riviera, or microelectronics – and not necessarily in that order – you’re going to be wanting to go to the Sophia Antipolis Microelectronics Forum taking place this year on October 2nd & 3rd.
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Tags: Antibes, ARM, Broadcom, Cadence, Cezanne, France, HP, IBM, Infineon, Intel, Matisse, Mentor Graphics, Nice, Picasso, SAME, Sophia Antipolis Microelectronics Forum, STMicro, Synopsys
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Tuesday, April 24th, 2012
There’s good news and bad news, in my opinion, with regards to Rajeev Madhavan, founder and CEO of Magma Design Automation, a company that was acquired by Synopsys on February 22, 2012.
The good news it that Rajeev is available to the press for candid interviews like the one included below. The bad news is Rajeev is not going to be part of the EDA landscape as he explores various options for the next phase of his life – and that means the industry will be just that much less interesting, at least for a while.
We spoke by phone in late February.
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Peggy: Hey, Rajeev, how are you doing?
Rajeev: I’m doing pretty much okay as I think about what’s next. I’ve got opportunities, and I’ve got other interests I can now pursue – most people rarely get this kind of opportunity in life, so I’m grateful.
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Tags: Aart de Geus, Andy Bechtolsheim, Cadence, EDA, Intel, M&A, Magma, Magma Design Automation, Mentor Graphics, Rajeev Madhavan, Synopsys, TSMC, Wally Rhines, Wind River
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Sunday, April 15th, 2012
Open Virtual Platforms are an idea whose time has arrived. That is, if you understand what they are. Certainly, if you’re reading this blog, you know what a virtual platform is.
“Platform virtual machines are software packages that emulate the whole physical computer machine, often giving multiple virtual machines on one physical platform.”
For additional clarity, check it out on Wikipedia, paying particular attention to the incredibly dense/complex table found there that attempts to catalog various virtual platforms, their origins, supporting organizations, and features.
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Imperas & Open Virtual Platforms
So, if that’s what virtual platforms are, then what are Open Virtual Platforms, OVPs?
Imperas – an enterprise founded in Silicon Valley in 2008 – would like you to understand and use OVPs. To do that, they are sponsoring a portal-based community called Open Virtual Platforms – a resource designed to help chip developers have access to various open source virtual platforms, or models, of various commonly used hardware platforms endemic to the embedded systems world.
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Tags: AMD, ARM, emulator, Freescale, Imperas, Intel, KVM, Larry Lapides, MIPS, Open Virtual Platform, Oracle, OVP, PalmPilot, Renases, Simon Davidmann, Synopsys, virtual machine, virtual platform, virtualization, VMware, Xilinx
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Thursday, March 29th, 2012
Here are the Top Ten reasons to be going to EDPS next week in Monterey:
10) Next week’s a lighter work week for most and the Monterey Peninsula is beautiful at any time of the year, but particularly in the spring.
9) The Electronic Design Process Symposium is in its 19th year, and everybody who’s anybody in EDA and its adjacencies has attended at one point or another.
Eight) The topics discussed at EDPS have always tracked the trajectory of the industry. In 2000, those topics included: deep sub-micron, distributed and web-based design methodologies, designer productivity, and maintaining modularity in an integrated design flow.
Here in 2012, technology evolution has driven a completely different set of topics: embedded processors, FPGAs, ESL, NUMA, EDA in the Cloud, Big Data and the Big Servers that serve them, low-power design, and 3d-ICs, among others.
7) Going to conferences is as much about conversations outside the sessions, as it is about presenting or listening within the sessions. EDPS is a boutique conference, where I promise you’ll have a chance for substantive conversations with the speakers, both inside and outside of the sessions.
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Tags: 3D-ICs, Altera, Arif Rahman, Azadeh Davoodi, Cadence, Deepak Sekar, Don MacMillen, Dusan Petranovic, EDPS, Electronic Design Process Symposium, Frank Schirrmeister, Gary Smith, Grant Martin, Hans Spanjaart, Herb Reiter, Ian Ferguson, James Colgan, Jim Hogan, Kiron Pai, Marc Greenberg, Mentor, Mike Hutton, Monterey Peninsula, Naresh Sehgal, Phil Marcoux, Qi Wang, Riko Radojcic, Samta Bansal, Sandeep Goel, Sangeeta Aggrwal, Sri Ganta, Steve Leibson, Steve Smith, Steven Pateras, Synopsys, Tom Spyrou
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Saturday, March 17th, 2012
When it comes to Westerns, nothing satisfies more than the one about long-time compadres getting together to do one last ride, one last round up, to take one last stand.
It satisfies, because it’s been years in the making and involves all aspects of the genre – long, lonely shots of distant horizons, fading references to the “exploration and settlement of previously untamed frontiers”, and a rich narrative of “rugged, self-sufficient individuals taming a savage wilderness with common sense and direct action.”
This particular type of Western also satisfies, because we know the players well – their faces, their mannerisms, how many notches they’ve got in their gun belts, and whether they normally ride alone or in a posse. (more…)
Tags: Aart deGeus, ARM, Barson & Monahan, Cadence, CEO Forecast Panel, Clint Eastwood, Code of the West, Cowboy, Ed Cheng, Ed Sperling, EDA, EDAC, Gradient Design Automation, Henry Fonda, John Ford, John Wayne, Lip-bu Tan, Mentor Graphics, Rawhide, Simon Segars, Synopsys, Unforgiven, Wally Rhines, Ward Bond, Western
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Thursday, March 15th, 2012
If you missed this week’s Blue Pearl Software workshop in Silicon Valley, you’re in luck – they’re holding it again on April 19th.
These workshops offer not only the opportunity to learn about Blue Pearl’s technologies, they’ll also let you brush up on your acronyms – FPGA, ASIC, SOC, CDC, SDC, SV, VHDL, and RTL – though not necessarily in that order.
Blue Pearl sells a suite of tools offering “comprehensive RTL analysis, clock-domain crossing [CDC] checks, and automated Synopsys Design Constraints [SDC] generation for FPGA, ASIC, and SOC designs.”
Release 6.0 was announced in February at DVCon 2012, where I spoke with Shakeel Jeeawoody, Director of Product Marketing at Blue Pearl.
Jeeawoody said, “We provide tools for linting, clock-domain crossing, and automated SDC generation – things people use to constrain their synthesis. Here in Release 6.0, a major new feature includes language coverage. (more…)
Tags: Altera, ASIC, Blue Pearl Software, CDC, clock-domain crossing, FPGA, RTL, RTL analysis, SDC, Shakeel Jeeawoody, SOC, Synopsys, Synopsys Design Constraints, SystemVerilog, Verific, Verilog, VHDL
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