Posts Tagged ‘STMicro’
Thursday, October 12th, 2017
DVCon Europe 2017 will be in Munich next week, a great destination for tourists and technologists alike. This is the fourth year the conference will occur in Europe, the original Silicon Valley based version now in its 27th year.
DVCon Europe General Chair Oliver Bell and I spoke this week by phone about the upcoming event; he was in Germany and I was in Northern California. I offered that Munich is a beautiful city, and he agreed.
“The conference will be in downtown Munich,” Bell said, “at the Holiday Inn. This is a really nice hotel, located near to Marienplaz, and easily reachable from public transportation.”
Bell then laughed and acknowledged that, as famous as the city’s Oktoberfest may be, it’s better that DVCon is being held several weeks after that particular annual exuberance has run its course. The city’s just that much more calm and enjoyable, he noted, after the hundreds of thousands of Oktoberfest revelers have returned to their normal pursuits.
Thursday, August 11th, 2016
It takes courage to re-launch an existing product rather than start from scratch, to announce a refreshed and updated offering as if it were something brand new. That’s certainly the case with Synopsys‘ recent release of TetraMAX II. It took courage to build on a franchise that first arrived on the scene not just in the last century, but in the last millennium.
And it was with this sentiment that Synopsys’ Robert Ruiz and I started a recent phone call to discuss the July news that TetraMAX II has arrived on the scene.
Ruiz began: “This is TetraMax II. We wrote the key engines from scratch, an effort that took the R&D team a full two years to complete. The goal was to get 10x faster and 25-percent fewer patterns.”
Thursday, September 5th, 2013
Herb Reiter, founder and president of eda2asic, has been in the semiconductor and EDA industry for 30+ years, including stints at Barcelona Design, Viewlogic, Synopsys, VLSI Technology, and National Semiconductor. In the last few years, Reiter’s work has focused on SOI, 2.5/3D ICs, and FinFET topics in semiconductor design and manufacturing. Straightforward enough, until you realize that these are significantly different ‘3D’ technologies, where ‘3D’ means different things to different people.
In a recent phone call, I asked Reiter to distinguish between what he calls the “three legs” of technology choices and to weigh in on which “leg” is most likely to succeed.
Fully-depleted SOI …
Per Reiter, “The original technology was partially-depleted SOI, a fairly thin film of silicon on top of a thin insulating layer. IBM came up with the idea, because substrate capacitance was slowing their chips down. They realized if they put in the insulating layer, they wouldn’t have to worry about substrate capacitance, because the oxide layer would insulate things.
“The planar transistor gate cannot reach all of the electrons in an 80-nanometer channel, cannot fully control the flow, and causes what we called ‘body-effect’ and ‘kink-effect’ design challenges. That’s why partially-depleted SOI was not widely used. So fully-depleted silicon on insulator, FDSOI, was introduced. It only has about a 20-nanometer active film on top of the oxide layer. The gate is sitting on top of the active film and can control all of the electrons passing through the source/drain channel, which is why it’s called fully-depleted SOI.
Thursday, June 27th, 2013
Atrenta VP Mike Gianfagna graciously extended an invitation to attend an event this evening in Grenoble, France. Jointly sponsored by CEA-Leti and Atrenta, Mike said the event was to be held on the CEA-Leti campus “in conjunction with Leti Innovations Days” and would “toast the progress Atrenta has made at its R&D facility in the city.”
It would have been great to have been there, as I was in Grenoble back in March 2011 when Atrenta first inaugurated its R&D center at the Micro and Nanotechnologies Innovation Center (MINATEC) in the city. The 2011 event was marked by a wonderful wine-enriched reception and a series of speakers articulating Atrenta’s vision in partnering with MINATEC. Those speakers included Atrenta CEO Ajoy Bose and STMicro’s Executive Vice President Philippe Magarshack, among others. You can see my original 2011 post below for more details.
Alternatively, if you want to know more about this evening’s reception in Grenoble, I have cut-and-pasted Mike Giafagna’s notes immediately below that he sent summarizing the event after the fact. It was not surprising to learn that Ajoy Bose spoke this evening, but to learn that Philippe Magarshack was also there, as he was in 2011, gives pause.
Thursday, December 13th, 2012
When it comes to stimulating, it doesn’t get better than stepping out of a session at IEDM in San Francisco to take a conference call from Glasgow. On Tuesday, December 11th, I stepped out of Session 9 and a presentation on spintronics to speak with Dr. Asen Asenov about a different device technology.
Asenov is a 20-year veteran of the University of Glasgow, where he serves as James Watt Professor of Electrical Engineering and heads up the Glasgow Device Modeling Group. He is also founder of Glasgow-based Gold Standard Simulations (GSS), a company that specializes in simulating statistical variability in nano-CMOS devices.
We spoke on December 11th because GSS announced that day the results of research “comparing the differentiation between metal gate first and metal gate last FDSOI [fully-depleted silicon-on-insulation] approaches, and comparing it to equivalent bulk MOSFETs.” Based on that work, the company announced that gate-last technology “offers significant advantages” over gate-first technology for devices built on 32- or 28-nanometer FDSOI, and noted that both nodes “significantly outpace equivalent bulk MOSFETS with respect to low-power SRAM design.”
Wednesday, August 1st, 2012
When Eric Filseth took over as CEO at Ciranova in September 2007, he was already a seasoned EDA veteran having clocked in an accumulated 17 years at Cadence at that point. Now here in 2012, Ciranova has just been acquired by Synopsys and it would seem Filseth’s organization has fulfilled the vision he articulated 5 long years ago.
Per Filseth in 2007: “The problems in analog are very hard. In the digital world, everything is very, very automated, but in the analog world it just isn’t that way. It’s still mostly done by hand and the concept of IP as you consider it in digital – take the RTL and port it to this design or that process – is not there. In analog, it’s still a manual thing for PLLs, and amplifiers, and so on.
“There’s been so much focus on digital SoCs, and things like place and route, there’s been a lot less time spent on analog. Now digital design works fantastically well. You can get a junior engineer with only a couple years’ experience designing thousands of gates a day.
“Just think about it. Over the last 20 years, we’ve had 4 or 5 generations of digital architectures developed but in analog, people are still doing things the way they did it 15 or 20 years ago. Clearly there‘s an opportunity here, and Ciranova is well positioned to take advantage of that opportunity.”
Thursday, July 19th, 2012
This week, Accellera Systems Initiative is announcing a new version of its SystemC library, Version 2.3 to be exact. There hasn’t been a new version since way back in 2005 with Version 2.1 (albeit 2.2, a bug-fix release, was published in 2006), so this is the culmination of a lot of hard work.
I spoke by phone with Accellera Systems Initiative Language Working Group Chair David Black, Senior Member of Technical Staff at Doulos, on July 17th.
Black explained, “The purpose of Version 2.3 is to reflect the latest version of IEEE Standard 1666 – to fundamentally demonstrate new features introduced into the SystemC standard, which includes TLM 2.0, previously an OSCI-only standard and now part of the IEEE standard. Interested parties can download the SystemC 2.3 library from the Accellera Systems Initiative website. This download includes several bug fixes, the latest TLM 2.0 and new SystemC features”
I asked Black who has participated in this work, and how often they meet. He said, “The Language Working Group of Accellera Systems Initiative includes all of the major EDA vendors – Cadence, Mentor, Synopsys, and Forte – and service providers such as Doulos and Circuit Sutra – and various members of the industry such as Intel, TI and STMicro, with everyone contributing a perspective.
“I am the Co-Chair of the SystemC Language Working Group along with Andy Goodrich [Forte Design Systems] and took over my position from Mike Meredith [also with Forte]. Key contributors also include Tor Jeremiassen [TI], John Aynsley and Alan Fitch [Doulos], Bishnupriya Bhattacharya [Cadence], Jerome Cornet [STMicroelectronics], Dr. Torsten Maehne [UPMC], Pat Sheridan and Bart Vanthournout [Synopsys], and Philipp Hartmann [OFFIS], along with many others.
Wednesday, June 6th, 2012
Each year, both Gary Smith and John Cooley provide a “Must See” list of companies they recommend attendees seek out and talk with at the Design Automation Conference. DAC 2012 was no different: Gary’s 2012 list had 27 companies and Cooley’s had over 80. Short of one, all of the companies on Gary’s list also appeared on John’s.
However, there were almost 200 exhibitors at DAC in San Francisco so clearly many companies exhibiting were not on these lists, which made for an interesting exercise: Go out onto the Exhibition Hall floor and only talk to companies who are not on the lists.
That’s what I did each day in San Francisco, walking up to booths without an appointment and in the process finding a host of articulate technologists, and their enterprises, which seem to exist under the radar at DAC. On Tuesday, June 5th, I spoke with 5 of them.
Tuesday, May 8th, 2012
And never more so than on Tuesday — especially this year, June 5th, when you’re going to have to make some terrible decisions about what to miss, and what not to miss.
First there’s the opening session in the morning when a boatload of awards are handed out, followed by the 2012 keynote. The Exhibition Hall won’t open until these things wrap up, so other than company meetings or company special-product announcement breakfasts, you should be able to be in the main theater at Moscone from 8:30 to 10:00 am or so.
Of course, worst case scenario: The opening session at DAC is always video-taped, so you could watch it at a later date after it’s uploaded to the DAC website but that’s hardly ideal.
This year’s main address will be delivered by ARM’s Mike Muller, “comparing the original ARM design of 1985 to those of today’s latest microprocessors … how far design has come and what EDA has contributed to enabling … systems, hardware, operating systems, and applications.” Then Muller plans to talk about 2020, how to get there, and what it will be like when we do. Conclusion? This stuff’s better heard in person than tape delayed. Go to the opening session, and plan not to regret it.
Thursday, May 3rd, 2012
The Sophia Antipolis Microelectronics Forum takes place every fall in the ‘Silicon Valley’ of Southern France, Sophia Antipolis, 5 miles inland from the beautiful Mediterranean city of Antibes.
Sophia Antipolis is about 20 minutes from the International Airport at Nice, with offices for approximately 800 high-tech companies – included among them: ARM, Broadcom, Cadence, HP, IBM, Infineon, Intel, Mentor Graphics, Nvidia, STMicro, and Synopsys – housed in a range of buildings set among the rolling hills of the enclave. Within that forested place and 800 enterprises, almost 40,000 people are employeed. There are also two college campuses in Sophia Antipolis, as well as restaurants, a golf course, multiple hotels, and a tennis institute.
In other words, if you’ve never been to the Cote d’Azur, never been to Nice or Antibes, if you think you’d love vistas across the wide blue Mediterranean Sea, want to learn more about good food, wine, Picasso, Matisse, ancient Greeks, the French Riviera, or microelectronics – and not necessarily in that order – you’re going to be wanting to go to the Sophia Antipolis Microelectronics Forum taking place this year on October 2nd & 3rd.