Posts Tagged ‘Verific’
Thursday, December 21st, 2017
Verific Design Automation in based in Alameda, not exactly Silicon Valley, but close enough to be within driving distance. The company has been in existence for almost 20 years and reports few competitors, if any. Instead, they see themselves as the de-facto standard for HDL language parsers, and as such can be found in just about every chip design flow.
In fact, according to Rick Carlson, Verific VP of Worldwide Sales, he’s more astonished with each passing day just how many places applications developed on top of Verific can be found. Not because he doubts the quality of the product, but because of the wide diversity of industries who are now developing chips.
Rick Carlson also knows a thing or two about building collegiality between the companies that constitute the EDA industry. He was one of the founders of the EDA Consortium 30 years ago, and the Phil Kaufman Award. We spoke at length last month.
Thursday, April 13th, 2017
Every industry needs advocates, and Bob Gardner served with distinction in that role for many years. When he passed away this week, the industry lost both an articulate spokesman, and someone who had a deep and nuanced understanding of how the unique group of companies involved in EDA and IP come together to provide the crucial underpinnings of a global semiconductor design chain.
Gardner’s most important industry-wide contributions, of course, came during his eight years as Executive Director of the EDA Consortium. He had, however, many years of leadership and involvement in a variety of companies prior to his EDAC assignment, including roles at Verific, Signetics/Philips, AMD, Exemplar Logic, Design Acceleration, Bridges2Silicon, and ITeX.
Given that background, Gardner was able to bring decades of corporate wisdom to his role at EDAC and used it wisely to help craft the mission and work of the Consortium. During his tenure, the organization expanded its membership, became even more pro-active in promoting the common agenda for member companies, and helped to expand the visibility of EDAC across North America and into Europe and beyond.
Tuesday, July 29th, 2014
There are two ways you could have talked to the young Vancouver-based company Invionics in June. Make your way to British Columbia, or seek them out in the Verific booth at DAC in San Francisco. The second option is how I got to chat with Invionics CEO Brad Quinton, and although our conversation amidst the organized chaos of DAC was brief, it left the impression of a company with a bold future ahead.
Per their website, the company’s products include “design tools, hardware IP and EDA development platforms.” However, Invionics also provides “experienced contract R&D to extend our products and IP, [which enables our] customers to quickly implement key functionality and gain competitive advantage for their products.”
In other words, Invionics is my favorite kind of company: A product company that’s also a services company. Of course, this is my evaluation and not necessarily theirs. Nonetheless, it was completely refreshing to talk to somebody at DAC who seems to look at things with a new perspective, an optimistic perspective that’s all about charting a new path going forward.
Thursday, March 15th, 2012
If you missed this week’s Blue Pearl Software workshop in Silicon Valley, you’re in luck – they’re holding it again on April 19th.
These workshops offer not only the opportunity to learn about Blue Pearl’s technologies, they’ll also let you brush up on your acronyms – FPGA, ASIC, SOC, CDC, SDC, SV, VHDL, and RTL – though not necessarily in that order.
Blue Pearl sells a suite of tools offering “comprehensive RTL analysis, clock-domain crossing [CDC] checks, and automated Synopsys Design Constraints [SDC] generation for FPGA, ASIC, and SOC designs.”
Release 6.0 was announced in February at DVCon 2012, where I spoke with Shakeel Jeeawoody, Director of Product Marketing at Blue Pearl.
Jeeawoody said, “We provide tools for linting, clock-domain crossing, and automated SDC generation – things people use to constrain their synthesis. Here in Release 6.0, a major new feature includes language coverage. (more…)