Posts Tagged ‘Samsung’
Thursday, December 21st, 2017
Verific Design Automation in based in Alameda, not exactly Silicon Valley, but close enough to be within driving distance. The company has been in existence for almost 20 years and reports few competitors, if any. Instead, they see themselves as the de-facto standard for HDL language parsers, and as such can be found in just about every chip design flow.
In fact, according to Rick Carlson, Verific VP of Worldwide Sales, he’s more astonished with each passing day just how many places applications developed on top of Verific can be found. Not because he doubts the quality of the product, but because of the wide diversity of industries who are now developing chips.
Rick Carlson also knows a thing or two about building collegiality between the companies that constitute the EDA industry. He was one of the founders of the EDA Consortium 30 years ago, and the Phil Kaufman Award. We spoke at length last month.
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Tags: AI, Apple, Applicon, ARM, Atari, Averant, Cadence, Calma, Commodore, Computervision, Daisy Systems, Dave Millman, EDA Consortium, EDA Systems, EDAC, Escalade, ESD Alliance, Go, IEEE 1801, IIT Chicago, Intel, Invionics, Mentor, Microsoft, Northstar, NVIDIA, Phil Kaufman Award, Qualcomm, RISC-V, Samsung, Sinclair, Steve Jobs, Synopsys, Synplicity, UPF 3.0, Valid Logic, Verific
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Thursday, November 2nd, 2017
ICScape is both an EDA company and an analog IP provider. The company’s EDA tools “cover the complete AMS design flow”, its SoC design tools are “point solutions for design closure”, and the ICScape IP catalog includes a variety of analog IPs.
Jason Xing is CEO of ICScape. Prior to co-founding the company in 2005, he was at Sun Microsystems for 7 years. Xing has two PhDs, in Computer Science from the University of Illinois at Urbana-Champaign and in Mathematics from the University of Louisiana. Xing is an accomplished technologist, and a well-informed observer of the semiconductor industry.
We spoke last week about his company and the future of the technology wherein he positions his offerings.
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Tags: HiSilicon, Hynex, ICScape, Jason Xing, Legend Designs Systems, LG, Marvel, Samsung, Tsinghua University, University of Illinois at Urbana-Champaign, University of Louisiana
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Thursday, August 31st, 2017
Amit Gupta is the quintessential entrepreneur in EDA. Even as he was graduating with degrees in EE and CS from University of Saskatchewan, he was co-founding Analog Design Automation, targeted at those who need tools to automate analog chip design. That was in 1999. The company was sold to Synopsys in 2004, and then Gupta co-founded Solido Design Automation in 2005.
This week, I had a chance to speak at length with Amit Gupta. The last time we conversed, it was at the January 2017 Kaufman Award dinner for Dr. Andres Strojwas in San Jose. That evening, Gupta was enthused about Solido’s access to high-quality engineering talent in Canada, and argued that the cost of living and quality of life in Saskatoon, where Solido is headquartered, more than compensate for any sense that Silicon Valley is the epicenter of the industry. His enthusiasm has only grown since that time.
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Tags: Amit Gupta, Analog Design Automation, Deloitte, Design Automation Conference, E3 Data Science, Eric Hall, ESD Alliance, finFET, GlobalFoundries, Gloria Nichols, Jeff Dyck, Mark Gilbert, NVIDIA, Qualcomm, Samsung, Saskatoon, SOI, Solido Design Automation, Sorin Dobre, Synopsys, Ting Ku, TSMC, UX design
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Thursday, May 5th, 2016
Luckily I arrived late to EDPS in Monterey on Friday, April 22, because I did not hear the introduction of the first keynote speaker or hear his name. A good thing, as it turns out. The speaker was a technologist who doesn’t embrace technology when it’s used as a tool for intrusions into our lives. He’s concerned about how our private facts have become part of the public fabric, accessible to anyone who knows how to navigate the Cloud.
And so, in the spirit of Life imitating Art, I’m not going to list his name here. That detail is fully available on the EDPS website, but it will not be articulated here. What will be articulated here, however, is the audience reaction to the Keynoter’s comments. The audience became part of the presentation, with the keynote address quickly morphing into a round table discussion, a group therapy session for technology whiz-kids who worry about the increasingly public nature of our private lives in this digital, always-connected era.
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Tags: Amazon, EDPS, Facebook, Google, IoT, Samsung, Tesla, US OPM
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Monday, March 23rd, 2015
The last time I spoke at length with OneSpin’s Dave Kelf, the conversation was all about the Cloud. This week we picked up where we left off, talking about the Cloud, but then moved on to the Wild West. Dave is quite taken with the idea that the current situation in EDA is on par with the Wild West, that mythical place where a lack of structure and entrenched establishment allows true innovators to run wild free. First however, we caught up with OneSpin and the Cloud.
Dave said, “These days, engineers cannot afford to stick their necks out. Neither their managers nor their corporate leadership want to take risks, and the engineers know it. Although engineers realize moving design to the Cloud makes sense, when they try to explain that to their bosses or corporate lawyers it often leads to legal discussions around the problems of having [propriety] IP leave the company’s server.
“At OneSpin, however, we are able to eliminate these issues by generating abstract verification proof problems that go to the Cloud for computation without the transfer of IP or even [identifiable markers], assuring our customers that the process is very secure. Moving to the Cloud means design teams will have access to infinite computing, with huge verification jobs running simultaneously.”
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Tags: Amazon, Assertion-Based Formal Verification, Broadcom, Cadence, Dave Kelf, Fujitsu, GlobalFoundries, Google, high-level synthesis, Intel, Microsoft, NXP, OneSpin, OneSpin 360 DV-Inspect, OneSpin 360 DV-Verify, Qualcomm, Raik Brinkmann, Samsung, Silicon Cloud, Sony, Synopsys, SystemC, TSMC
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Tuesday, June 10th, 2014
UMass Amherst’s Sandip Kundu moderated a Thursday afternoon panel at DAC entitled, ‘Designing on Advanced Process Nodes: How many re-spins should you plan for?’
In concert with his four panelists, Broadcom’s Ajat Hukkoo, Intel’s Ashu Bakhle, Samsung’s Hong Hao, and GlobalFoundries’ Luigi Capodieci, Kundu laid out qualitative motivations and quantitative guidelines for predicting how many re-spins can be expected when a design targets next-generation geometries.
Prof. Kundu began with an homage to the costs and challenges: “Chips are expensive to develop, the Spice models are expensive to develop, and the first-pass and second-pass models often are not working.”
It’s within this environment of uncertainty, Kundu said, that designers and their managers are having difficulty predicting how many re-spins will be needed to get things right, and thus budgets and schedules are equally unpredictable.
Ajat Hukkoo agreed: “At Broadcom, every time we migrated from one node to another, the partitioning [of the design] had to be re-evaluated for electrical considerations and costs.
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Tags: Ajat Hukkoo, Ashu Bakhle, Broadcom, DAC 2014, GlobalFoundries, Hong Hao, Intel, Luigi Capodieci, Samsung, Sandip Kundu, University of Massachusetts Amherst
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Thursday, January 23rd, 2014
Long, long ago in a galaxy far, far away the EDA Empire began and quickly coalesced into several big players and a band of plucky startups constantly attempting to compete and stay viable.
Back in that halcyon era, Rick Carlson and Dave Millman decided to get those startups to pull as one, to try to keep the industry open and progressing, to protect the EDA industry as a place where new ideas could see the light of day and offerings from small companies could compete on a level playing field against those from the big players.
To do that, Rick and Dave came up with the idea for a consortium of Independent Design Automation Companies, IDAC, and put out the word to like-minded colleagues that this new group would benefit everybody. Creating IDAC proved more difficult than they had hoped, so letting pragmatism rule the day they approached Joe Costello for help, then CEO of Cadence, even though that meant working with one of the ‘big guys’ and hence, EDAC came to fruition.
To hear the rest of the story per Rick, recounted in a phone call in December, click here.
To hear the story recounted by Joe Costello, read below. I spoke with both Joe and Rick together on a conference call in mid-January.
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Revolution from within …
Joe began: “Rick told me he’s concerned that in his recent conversation with you about the history of EDAC, he may have sounded too harsh. I said that’s not possible, because the truth about the industry is quite harsh. Just thinking about it makes my blood boil.
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Tags: all-you-can-eat EDA, Broadcom, Cadence, Dave Millman, EDAC, EDAC Interoperability Lab, IDAC, Intel, Joe Costello, Mentor Graphics, Qualcomm, Rick Carlson, Samsung, Synopsys
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Thursday, September 5th, 2013
Herb Reiter, founder and president of eda2asic, has been in the semiconductor and EDA industry for 30+ years, including stints at Barcelona Design, Viewlogic, Synopsys, VLSI Technology, and National Semiconductor. In the last few years, Reiter’s work has focused on SOI, 2.5/3D ICs, and FinFET topics in semiconductor design and manufacturing. Straightforward enough, until you realize that these are significantly different ‘3D’ technologies, where ‘3D’ means different things to different people.
In a recent phone call, I asked Reiter to distinguish between what he calls the “three legs” of technology choices and to weigh in on which “leg” is most likely to succeed.
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Fully-depleted SOI …
Per Reiter, “The original technology was partially-depleted SOI, a fairly thin film of silicon on top of a thin insulating layer. IBM came up with the idea, because substrate capacitance was slowing their chips down. They realized if they put in the insulating layer, they wouldn’t have to worry about substrate capacitance, because the oxide layer would insulate things.
“The planar transistor gate cannot reach all of the electrons in an 80-nanometer channel, cannot fully control the flow, and causes what we called ‘body-effect’ and ‘kink-effect’ design challenges. That’s why partially-depleted SOI was not widely used. So fully-depleted silicon on insulator, FDSOI, was introduced. It only has about a 20-nanometer active film on top of the oxide layer. The gate is sitting on top of the active film and can control all of the electrons passing through the source/drain channel, which is why it’s called fully-depleted SOI.
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Tags: 2.5/3D ICs, AMD, Amkor, Chenming Hu, eda2asic, Elpida, FDSOI, finFET, Herb Reiter, Hybrid Memory Cube, Hynix, IBM, Intel, Micron, partially-depleted SOI, Samsung, SanDisk, Soitec, STMicro, Tezzaron, Toshiba, TSMC, Xilinx
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Tuesday, June 4th, 2013
The only thing most people remember about Tuesdays at DAC are the parties. You’re a success if you attended at least two, less than a success if you only attended one, and guaranteed immortality if you attended more than three.
Of course, other things happen on Tuesdays at DAC – early morning breakfasts where sincere technologists present and/or opine about somber challenges facing the industry, the plenary session, presentation of multiple awards, pavilion panels, mid-day luncheons, afternoon sessions, posters, and many, many hours logged in by booth staff talking and talking and talking to customers, potential customers, and general industry hangers-on looking for free give-aways.
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Tags: Aart de Geus, Bob Madge, Cadence/Denali, CEDA, Ed Lee, Freescale, GlobalFoundries, Gutenberg, Hermann Kopetz, IBM, J.C. Parker, Jose Nunez, Kee Sup Kim, LSI, Rex Berridge, Samsung, Soha Hassoun, Solomon Golomb, Stars of IP, Stephen Woo, Synopsys
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Thursday, March 14th, 2013
From the podium in San Jose’s DoubleTree Hotel, Jasper Design Automation President & CEO Kathryn Kranen introduced tonight’s EDAC CEO Forecast Event as being “practically perfection” and she was right. With 97 people in the room, the event ran for 97 minutes and the audience [undoubtedly] gave the panel discussion a 97% approval rating. Kudos to all involved, including EDAC for hosting, and OCP-IP, Mod Marketing, and the DoubleTree for sponsoring the event.
Kranen started off the evening by bragging on good news out of EDA: It’s up and to the right for revenue in the industry, with a 4.9 percent increase between 3Q11 and 3Q12. She cited increased stock valuations over the last year for ARM [37%], Cadence [30%], Mentor [26%], PDF Solutions [98%], and Synopsys [17%] as an indication of the viability of EDA as an investment vehicle: If you’d put $100 into each of these companies a year ago, she said, you would have netted a 41% increase in a portfolio today worth $706.90, beating out other investment indices such as the NASDAQ and S&P 100 over the same time period.
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Tags: 14nm FinFET, Aart de Geus, Ansys, Apple, ARM, Cadence, Computer History Museum, DAC, DATE, DoubleTree, EDA Reunion, EUV, Google, Gordon Moore, Jasper Design Automation, Jim Hogan, Joe Costello, Kathryn Kranen, Lip-bu Tan, Mentor Graphics, MOD Marketing, Nimbic, OCP-IP, Raul Camposano, Rich Valera, Samsung, Simon Segars, Synopsys, Wally Rhines
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