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 EDACafe Editorial
Peggy Aycinena
Peggy Aycinena
Peggy Aycinena is a contributing editor for EDACafe.Com

Herb Reiter: The three-legged stool of Technology Choices

September 5th, 2013 by Peggy Aycinena

Herb Reiter, founder and president of eda2asic, has been in the semiconductor and EDA industry for 30+ years, including stints at Barcelona Design, Viewlogic, Synopsys, VLSI Technology, and National Semiconductor. In the last few years, Reiter’s work has focused on SOI, 2.5/3D ICs, and FinFET topics in semiconductor design and manufacturing. Straightforward enough, until you realize that these are significantly different ‘3D’ technologies, where ‘3D’ means different things to different people.

In a recent phone call, I asked Reiter to distinguish between what he calls the “three legs” of technology choices and to weigh in on which “leg” is most likely to succeed.

Fully-depleted SOI …

Per Reiter, “The original technology was partially-depleted SOI, a fairly thin film of silicon on top of a thin insulating layer. IBM came up with the idea, because substrate capacitance was slowing their chips down. They realized if they put in the insulating layer, they wouldn’t have to worry about substrate capacitance, because the oxide layer would insulate things.

“The planar transistor gate cannot reach all of the electrons in an 80-nanometer channel, cannot fully control the flow, and causes what we called ‘body-effect’ and ‘kink-effect’ design challenges. That’s why partially-depleted SOI was not widely used. So fully-depleted silicon on insulator, FDSOI, was introduced. It only has about a 20-nanometer active film on top of the oxide layer. The gate is sitting on top of the active film and can control all of the electrons passing through the source/drain channel, which is why it’s called fully-depleted SOI.

“FDSOI has none of the design challenges partially-depleted SOI exhibits, but the blank SOI wafers are much more difficult to manufacture. In return, designers reap the benefits of reduced/eliminated substrate capacitance and short-channel effects. However, the designer has to ask how much cost and time there is to ramping up to manufacturing FDSOI?

“This is a question that Soitec asked years ago. The price for a partially-depleted wafer was over $1000 – almost 10x the cost of regular bulk CMOS wafers – and a barrier for adoption, because many applications were not able to carry the added costs just to enjoy the benefits. That’s why we only ended up with partially-depleted SOI at IBM, AMD, and various other companies.

“However, as the target has become high-speed apps with better power constraints, those targeted at partially-depleted SOI were difficult to design, because the transistor-level effects required a lot of extra care from the designers.

“The beauty of FDSOI is that the design requirements are just like bulk silicon and are almost totally transparent to the designers. If based on FDSOI with the thin active film fully depleted, it looks like bulk silicon – not 100-percent the same, but 99-percent equivalent, so it practically doesn’t matter.

“You can actually take a bulk design and simply transfer it to an FDSOI wafer. In the manufacturing process, FDSOI actually requires fewer steps in manufacturing and less processing time in the wafer fab. If you fine tune your bulk design for FDSOI, you can reap all its benefits, fully.

“People ask whether you get all or just some of those additional wafer costs back. I would argue that most of it comes back in wafer manufacturing cost savings. The official number from Soitec regarding FDSOI wafer costs says they are about $500/wafer, so the difference is no longer 10x versus bulk silicon wafers as it was with partially-depleted SOI, but only 2-to-3x.

“And consider the savings in the fab, where you have fewer process steps and less processing time. Also, remember that with each step in manufacturing, the yield decreases – the bottom line is that FDSOI is becoming really cost competitive for most apps.

“[In fact], you may hear more companies than just STMicro are doing a lot of designs on FDSOI, because in addition to cost equivalents, they get significant power savings and speed up.”

2.5/3D ICs …

Per Reiter, “2.5/3D has been around for a number of years, and I’ve been personally involved for 5 years. It’s really catching on now, and there are two kinds: 2.5D and 3D ICs.

“First of all, there’s the Xilinx kind that’s strictly high-end, something like 30,000 or 40,000 connections between the die and the interposer. It requires a fine geometry and silicon interposers, which is more costly than glass or organic interposers.

“Silicon interposer is the most costly, but allows thin geometries, lots of interconnect layers, and is basically the high-end solution. Organic or glass interposers can offer lower cost – especially organic, which is really catching on in various places if a design doesn’t need 10,000 connections.

“Remember when Intel introduced the Haswell chip? It’s not really one die, but two pieces of silicon, side-by-side on the package substrate. Intel is using this concept quite a lot – using the substrate of the package for interconnections, because their applications don’t require that many interconnects between the CPU and the memory. Fairly wide pitches, and course geometries don’t need an interposer.

“However, the package substrate becomes more costly. You save on substrate cost and gain more design flexibility if you’re using an interposer in between the actual die and the package substrate. So much about 2.5D ICs.

“The 3D vertical Flash memory Samsung recently introduced is really a hot thing, because it makes all the stacking happen in the fab. This eliminates the need for TSVs and wafer thinning, some of the current ecosystem challenges.

“Samsung’s 3D memory should have pretty good yield and may use existing fabs instead of new ones. They stack memory layers on each other, a brilliant idea to serve their target market, Flash, and a very, very high growth opportunity. Micron promises a similar solution for 2014. Toshiba and SanDisk are also developing a similar concept for introduction in 2014/15.

“In addition, Micron and Samsung, the founding members of the Hybrid Memory Cube Consortium, are finalizing the development of the Hybrid Memory Cube (HMC), with 4 or 8 layers of TSV-interconnected DRAMs and a logic chip to control the stack, also for introduction early 2014.

“Like the HMC – for logic combined with memory or analog, or MEMS structures on top of the logic die, we will continue to rely on TSVs as interconnects between layers, as TSVs are getting thinner and are already yielding well.

“Two years ago, the major challenge was how to fill them – the 10-to-1, height-to-width ratio – and how to deal with the mechanical and thermal issues. But that was 2 years ago. Now those problems have been solved and people are talking about making the 5-micron diameter TSVs much thinner, eventually 2 microns or less for 50 or 40 micron thin wafers.

“Basically, the manufacturing equipment can fill the vias better, using improved materials and temperature profiles. It’s been a lot of leg work in both physics and chemistry, but the industry has met the requirements for 3D TSVs.

“A number of large companies have benefited from this progress – among them, IBM, Samsung, Micron, TSMC, Hynix, Intel, Amkor, and Elpida – with all of these key players are using this technology to design circuits more efficiently, using 5-micron or thinner TSVs.

“[In fact], Tezzaron will tell you that they are using 1.2 micron diameter TSVs in their many designs for customers. Both bandwidth and latency improve by an order of magnitude with 3D-IC stacks, compared to PCB solutions.

“In today’s PCB centric designs the CPU still need to send the signals through its I/Os, through the bonding wire, the package pin, across the PCB to the memory, through the package pin, the bonding wire, and the input buffer of the memory. The data comes back in the same way. That’s why people call this slow and power-hungry interconnect method the ‘Memory Wall’. The really fast components, CPU and memory, are having to slow down a lot to communicate with each other.

“Which leads us to FinFETs.”

FinFETs …

Reiter said, “The FinFET concept is similar to fully-depleted SOI. In FDSOI, the channel is lying flat with the gate on top. In FinFETs you now have the active channel carrying electrons upright like a fin, with the gate wrapped around it. This means that, like FDSOI, the gate can fully deplete the channel, minimize leakage, and also offer high on-current.

“FinFETs’ extremely low leakage, compared to any planar transistor, is excellent. Therefore, we will be able to expand the battery life on all of our mobile devices and save cooling in data centers.

“Yes, there is a question about the cost of the FinFET. I am working currently with a few companies on this issue, and what I am seeing is that there is still a lot of learning needed. How to get the most mileage out of the FinFET still requires a lot of work by designers and manufacturers.

“Right now, I am reluctant to give an answer as to when FinFETs will become mainstream technology – we still need to run a number of designs to get good data.

“I appreciate that people like Professor Chenming Hu, the Father of the FinFET, believes that in the long run there will be no additional cost in manufacturing FinFETs compared to planar transistors, and I certainly hope that is the case.

“But keep in mind that it is not just manufacturing the FinFETs that is impacting yield and cost. Today’s ICs have 10 or more tightly spaced metal layers on top of the transistors, which also impact the situation. This metal system on top cannot be made much smaller than in planar designs, so the die size may remain the same or similar.

“There are a number of variables you have to work through before you can theoretically reason what the costs of the die will be. If there will be savings in addition to less leakage and longer battery life, that will offset the additional costs that may arise around design and manufacturing. Plus, keep in mind that questions around EUV are also complicating things. So the decision to use FinFETs is not a black-and-white question today.

“We have always had several years of production ramp-up before we could really understand a technology and whether it was equivalent or better than a previous technology. New materials and equipment introduce new challenges and sometimes we get caught by unexpected effects causing delays and surprises.

“I was one of the first to work on programmable logic, on gate arrays, on cell-based technology, on 3D ICs, and am now engaging with FinFETs – so I have always been on the bleeding edge. It has been my experience that when there are challenges, designers and manufacturers rise to the occasion and solve the problems.”

Capital intensive & risk prone …

Reiter concluded, “The next 2 or 3 years, as we ramp up volume production on FinFETs and 3D ICs and SOI, all of these efforts will be capital intensive and risk prone. Investors in general can be very unforgiving, and sometimes even discourage innovation. Unlike during the boom times, if an executive makes a wrong decision, he or she cannot just walk across the street to a different company and become a leader there.

“If the economics are not there to push a new technology forward, it can be compelling for a company to stay with the existing technology until customers demand something new. And usually that only happens when a customer is convinced that if they don’t make the change, their competition will get ahead of them.

“As always, my biggest worry about these new technologies is getting the money and time to resolve all of these challenges. That’s the key reason I have been looking at all of these 3D technologies, and the opportunity to combine them with existing manufacturing nodes. Until there is a clear winner in all of these technologies, and the individual strengths are clearly matched with specific applications, companies will continue to move forward cautiously.

“At least for now, executives and designers can still choose from a three-legged stool!”


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