Posts Tagged ‘RISC-V’
Wednesday, January 9th, 2019
 In 1999, artificial intelligence was barely out of the concept stage and the telecommunications industry had just ratified the IEEE 802.11 a and b wireless standards. No one in the semiconductor industry used the term open source. Verific was founded that year to provide VHDL and Verilog parsers and elaborators to serve as the common front-end to newly developed EDA tools.
As Verific celebrates its 20th anniversary in 2019 with its software in production and development flows throughout the semiconductor industry worldwide, the technology horizon looks dazzling. Verification companies are announcing new tools, technologies and methodologies to support chip designs for artificial intelligence, machine learning, 5G wireless, and RISC-V to name a few.
Tags: 5G wireless, 802.11, Predictions, RISC-V
No Comments »
Thursday, December 21st, 2017
Verific Design Automation in based in Alameda, not exactly Silicon Valley, but close enough to be within driving distance. The company has been in existence for almost 20 years and reports few competitors, if any. Instead, they see themselves as the de-facto standard for HDL language parsers, and as such can be found in just about every chip design flow.
In fact, according to Rick Carlson, Verific VP of Worldwide Sales, he’s more astonished with each passing day just how many places applications developed on top of Verific can be found. Not because he doubts the quality of the product, but because of the wide diversity of industries who are now developing chips.
Rick Carlson also knows a thing or two about building collegiality between the companies that constitute the EDA industry. He was one of the founders of the EDA Consortium 30 years ago, and the Phil Kaufman Award. We spoke at length last month.
(more…)
Tags: AI, Apple, Applicon, ARM, Atari, Averant, Cadence, Calma, Commodore, Computervision, Daisy Systems, Dave Millman, EDA Consortium, EDA Systems, EDAC, Escalade, ESD Alliance, Go, IEEE 1801, IIT Chicago, Intel, Invionics, Mentor, Microsoft, Northstar, NVIDIA, Phil Kaufman Award, Qualcomm, RISC-V, Samsung, Sinclair, Steve Jobs, Synopsys, Synplicity, UPF 3.0, Valid Logic, Verific
No Comments »
Wednesday, June 14th, 2017
The following transcript is from a panel that’s not showcasing at the Design Automation Conference next week in Austin. It was submitted as an idea last Fall, but was declined by conference organizers.
Why was that? Is the idea of crowd sourcing chip design a tad too open source-ish for the EDA establishment, too community based and innovative? Who knows.
The panel discussion took place, nonetheless, several weeks ago and is available below. It’s a conversation between eFabless Co-founder & CTO Mohamed Kassem and TopCoder Co-founder Jack Hughes, now Director of Tongal and member of the eFabless Board.
Per the eFabless website, the company “applies collective and multidisciplinary community knowledge to all aspects of semiconductor product development.”
Per the TopCoder website, this company has a “community of over 1,000,000 design and technology experts [providing] on-demand capability, bandwidth, and velocity so you can do more.”
The dialog below reflects both Jack Hughes’ and Mohamed Kassem’s deep knowledge around the issues of building design communities, open-source technology, and crowd sourcing design.
(more…)
Tags: Amazon, Apple, ARM, Crowd sourcing, DAC 2017, eFabless, Facebook, Fitbit, GitHub, Google, GoPro, Jack Hughes, Linux, mixed-domain knowledge, Mohamed Kassem, NVIDIA, RISC-V, Tongal, TopCoder, Wally Rhines, X-Fab
No Comments »
|
In 1999, artificial intelligence was barely out of the concept stage and the telecommunications industry had just ratified the IEEE 802.11 a and b wireless standards. No one in the semiconductor industry used the term open source. Verific was founded that year to provide VHDL and Verilog parsers and elaborators to serve as the common front-end to newly developed EDA tools.
