Posts Tagged ‘Mentor’
Thursday, December 21st, 2017
Verific Design Automation in based in Alameda, not exactly Silicon Valley, but close enough to be within driving distance. The company has been in existence for almost 20 years and reports few competitors, if any. Instead, they see themselves as the de-facto standard for HDL language parsers, and as such can be found in just about every chip design flow.
In fact, according to Rick Carlson, Verific VP of Worldwide Sales, he’s more astonished with each passing day just how many places applications developed on top of Verific can be found. Not because he doubts the quality of the product, but because of the wide diversity of industries who are now developing chips.
Rick Carlson also knows a thing or two about building collegiality between the companies that constitute the EDA industry. He was one of the founders of the EDA Consortium 30 years ago, and the Phil Kaufman Award. We spoke at length last month.
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Tags: AI, Apple, Applicon, ARM, Atari, Averant, Cadence, Calma, Commodore, Computervision, Daisy Systems, Dave Millman, EDA Consortium, EDA Systems, EDAC, Escalade, ESD Alliance, Go, IEEE 1801, IIT Chicago, Intel, Invionics, Mentor, Microsoft, Northstar, NVIDIA, Phil Kaufman Award, Qualcomm, RISC-V, Samsung, Sinclair, Steve Jobs, Synopsys, Synplicity, UPF 3.0, Valid Logic, Verific
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Thursday, September 21st, 2017
Silicon Valley based Blue Pearl Software is the quintessential EDA company: privately held, run by a seasoned team of EDA experts, and with a portfolio that includes tools for generating timing constraints, CDC analysis, both synchronous and asynchronous, RTL verification tools for methodology standards and design rules, and design management tools.
Similarly, Blue Pearl’s Ellis Smith is the quintessential CEO in EDA. Before founding his current company, Smith was CEO and President of Orora Design Technologies, CEO at TransEDA through that company’s IPO in 2000, and CEO at Exemplar Logic through its merger with Mentor Graphics in 1995. His experience also includes a stint as CEO at CrossCheck Technology, and years spent at Duet Technologies, CADAM, Versatec, Dictaphone, and 3M. Pretty much the whole history of the EDA industry in one CV.
It would be an excellent idea to sit down for a very long conversation with Ellis Smith to discuss his take on the history of this oh-so-interesting industry. Unfortunately, time was of the essence when I did get the chance to talk with him earlier this month, and the focus was principally on Blue Pearl.
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Tags: Altera, Blue Pearl Software, Cadence, ESD Alliance, Mentor, MicroSemi, Synopsys, Xilinx
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Thursday, September 22nd, 2016
Last year a blog was posted in this space talking about tools for PCB design: PCB Tools, Part 1: Zuken, Mentor, Cadence, Altium. Lengthy and detailed, that discussion included commentary on the state of the art, and the market, for PCB design tools.
Now it’s time to assemble Part 2 of the discussion, which will be posted here in early November. This second installment intends to include input from more than just the four companies in the first article.
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Tags: Altium, Cadence, Mentor, PCB Design, Zuken
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Thursday, August 18th, 2016
As of August 17th, when they posted financial results for Q3_2016, Synopsys is reporting somewhere in the neighborhood of $1 billion in cash and cash equivalents. As prudent as it may be to save for a rainy day, here’s something a bit more creative the company could do with a portion of that cash: Buy OneSpin.
Why? Because OneSpin offers something that Synopsys doesn’t have – a market-leading position in formal verification. OneSpin would bring that to Synopsys, along with a strong, well-established track record and proven customer engagements across European, North American and Asian markets.
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Tags: Cadence, EVE, Jasper, Mentor, OneSpin, Palladium, Synopsys, Veloce
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Thursday, December 10th, 2015
If Wednesday night’s EDAC event at their headquarters in San Jose is any indication, things ain’t so good in the EDA ‘hood. There are no investors, no startups, no energy, no room for innovation, no luster, and ergo no young people.
Although, Jim Hogan – who shared the evening’s stage with Ansys/Apache VP & GM John Lee – said that if you think EDA’s bad, you should look at Google. According to Hogan, the luster’s gone at Google as well, buses transporting techies from Silicon Valley to their habitats elsewhere are running half empty, and nobody wants to be there anymore. The Google glam is gone, per Hogan, even though the overpaid youngsters he knows who work there are regularly pulling in salaries of $500k and holding an additional $500k in stock.
Hogan had no answer for how EDA was going to match those perks, but both he and Lee agreed that everything’s cyclical and therefore if everybody can just hold on for another 5 years, EDA will be back in fashion.
Meanwhile, it still ain’t so good in the EDA hood … or is it?
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Tags: Ansys, Apache, Avanti, Cadence, CMU, DAC, EDA, EDAC, Google, Jerry Hsu, Jim Hogan, John Lee, Mentor, Nassda, Roh Rohrer, Synopsys
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Thursday, September 13th, 2012
Samsung Venture Investment Corp. has just put $4 million into Carbon Design Systems in conjunction with the debut of a new strategic partnership between the two companies.
Per the September 12th Press Release: “Funds from the strategic investment will be used as working capital and will support Carbon’s ongoing development of leading tools in the ESL design space, including its fast, accurate virtual prototypes. Initiatives will be undertaken to expand the reach of Carbon’s fast, accurate virtual prototypes.”
 I spoke with Bill Neifert, Carbon’s founder, CTO and VP of Business Development on the day of the announcement. He was amazingly relaxed, a clear indication that the Samsung-Carbon partnership is a logical outcome of a long-term relationship between the organizations:
“Samsung been a heavy user of our tools for quite some time, and has been looking for ways to take even more advantage of that situation – to speed up product introductions, something that everyone’s trying to do in that marketplace.
“Today’s announcement is part of a Samsung initiative to advance their SoC design methodologies. They have both the resources and expertise today to innovate and are looking to us to help them with that. This is also a nice partnership for us, of course. It will help us share our methodology in a broader fashion.”
I asked if Samsung’s investment will jettison Carbon into an even better market position.
Bill said, “Yes, but this is a true partnership. It’s not just about money for Carbon, but about having additional access to Samsung’s time, expertise, and technology. Samsung wants to make better products, and enhancing our technology will also expand their customer base.”
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Tags: ARM, Bill Neifert, Cadence, Carbon Design Systems, Carbon IP Exchange, Denali, Mentor, Synopsys, Virtual Prototyping
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Thursday, July 19th, 2012
This week, Accellera Systems Initiative is announcing a new version of its SystemC library, Version 2.3 to be exact. There hasn’t been a new version since way back in 2005 with Version 2.1 (albeit 2.2, a bug-fix release, was published in 2006), so this is the culmination of a lot of hard work.
I spoke by phone with Accellera Systems Initiative Language Working Group Chair David Black, Senior Member of Technical Staff at Doulos, on July 17th.
Black explained, “The purpose of Version 2.3 is to reflect the latest version of IEEE Standard 1666 – to fundamentally demonstrate new features introduced into the SystemC standard, which includes TLM 2.0, previously an OSCI-only standard and now part of the IEEE standard. Interested parties can download the SystemC 2.3 library from the Accellera Systems Initiative website. This download includes several bug fixes, the latest TLM 2.0 and new SystemC features”
I asked Black who has participated in this work, and how often they meet. He said, “The Language Working Group of Accellera Systems Initiative includes all of the major EDA vendors – Cadence, Mentor, Synopsys, and Forte – and service providers such as Doulos and Circuit Sutra – and various members of the industry such as Intel, TI and STMicro, with everyone contributing a perspective.
“I am the Co-Chair of the SystemC Language Working Group along with Andy Goodrich [Forte Design Systems] and took over my position from Mike Meredith [also with Forte]. Key contributors also include Tor Jeremiassen [TI], John Aynsley and Alan Fitch [Doulos], Bishnupriya Bhattacharya [Cadence], Jerome Cornet [STMicroelectronics], Dr. Torsten Maehne [UPMC], Pat Sheridan and Bart Vanthournout [Synopsys], and Philipp Hartmann [OFFIS], along with many others.
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Tags: Accellera, Accellera Systems Initiative, Alan Fitch, Andy Goodrich, Bart Vanthournout, Bishnupriya Bhattacharya, Cadence, David Black, Doulos, Dr. Torsten Maehne, Forte, Jerome Cornet, John Aynsley, Mentor, Mike Meredith, OFFIS, OSCI, Pat Sheridan, Philipp Hartmannm, STMicro, Synopsys, SystemC Library 2.3, Tor Jeremiassen, UPMC
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Wednesday, July 18th, 2012
To get to MathWorks’ corporate headquarters outside Boston, take the Red Line to the Orange Line to Back Bay Station. Take the Commuter Rail to Natick, cross the bridge over the tracks, walk north along leafy Walnut Street for a mile and a quarter, turn left onto Route 9, and cross the grass to Apple Hill Drive. Turn left into the parking lot of the company’s campus, pick your way through the construction going on there, and look for the main reception building across from the big parking structure.
 If you do all of this, and it’s 90+ degrees with 60% humidity, you’ll be totally drenched by the time you walk into the cool of the MathWorks headquarters. But no worries; the very nice person at the reception desk will send you down the hall to the closest break room where you can get a tall drink from the beverage dispenser and bring it back to the reception area to rest, recuperate, and prepare for your meeting with Ken Karnofsky.
Okay, two points of interest here: a) MathWorks is different. It’s headquartered in a residential neighborhood, not a commercial park; and b) the welcome is relaxed and not the high-pressure stuff of Silicon Valley.
Two additional points of interest: c) MathWorks is expanding. They’ve got 2400 employees currently, with an additional 200 job openings! Their Natick campus may offer a calm retreat from a humid Massachusetts afternoon, but it’s not a calm retreat from the world because when you’re there, MathWorks feels to be at the center of the world.
And d) MathWorks is definitely an EDA company, even though they don’t belong to EDAC and they don’t exhibit at DAC (although they have exhibited in the past). If you design chips, MathWorks’ MATLAB and Simulink is the gateway into your design. When it comes to EDA, MathWorks is most definitely the elephant in the room.
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Tags: Cadence, Cleve Moler, EEsof, Forte, HL Systems, Jack Horgan, Jack Little, John Stickley, Ken Karnofsky, MathWorks, MATLAB, Mentor, Natick, Simulink, Synopsys, Wade Stone
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Thursday, March 29th, 2012
Here are the Top Ten reasons to be going to EDPS next week in Monterey:
10) Next week’s a lighter work week for most and the Monterey Peninsula is beautiful at any time of the year, but particularly in the spring.
9) The Electronic Design Process Symposium is in its 19th year, and everybody who’s anybody in EDA and its adjacencies has attended at one point or another.
Eight) The topics discussed at EDPS have always tracked the trajectory of the industry. In 2000, those topics included: deep sub-micron, distributed and web-based design methodologies, designer productivity, and maintaining modularity in an integrated design flow.
Here in 2012, technology evolution has driven a completely different set of topics: embedded processors, FPGAs, ESL, NUMA, EDA in the Cloud, Big Data and the Big Servers that serve them, low-power design, and 3d-ICs, among others.
7) Going to conferences is as much about conversations outside the sessions, as it is about presenting or listening within the sessions. EDPS is a boutique conference, where I promise you’ll have a chance for substantive conversations with the speakers, both inside and outside of the sessions.
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Tags: 3D-ICs, Altera, Arif Rahman, Azadeh Davoodi, Cadence, Deepak Sekar, Don MacMillen, Dusan Petranovic, EDPS, Electronic Design Process Symposium, Frank Schirrmeister, Gary Smith, Grant Martin, Hans Spanjaart, Herb Reiter, Ian Ferguson, James Colgan, Jim Hogan, Kiron Pai, Marc Greenberg, Mentor, Mike Hutton, Monterey Peninsula, Naresh Sehgal, Phil Marcoux, Qi Wang, Riko Radojcic, Samta Bansal, Sandeep Goel, Sangeeta Aggrwal, Sri Ganta, Steve Leibson, Steve Smith, Steven Pateras, Synopsys, Tom Spyrou
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Friday, February 17th, 2012
Here’s your February Pop Quiz.
******************
1 – DVCon 2012 starts on February 27th. The conference was first held in _____.
a) 1989
b) 1995
c) 1998
d) 2003
2 – The IEEE Standards Association [IEEE-SA] oversees approximately _____ standards and _____ standards under development.
a) 500, 900
b) 800, 600
c) 900, 500
d) 700, 900
3 – The IEEE Standard associated with VHDL is _____.
a) IEEE Std 1064
b) IEEE Std 1076
c) IEEE Std 1164
d) IEEE Std 1176
4 – Accellera merged with _____ in 2011.
a) VSIA
b) OSCI
c) OCP-IP
d) OVI
5 – DVCon is managed by MP Associates, the same group that manages _____.
a) ICCAD
b) DesignCon
c) Semicon
d) ISQED
6 – The 2007 General Chair of DVCon was _____.
a) Tom Fitzpatrick
b) Stephen Bailey
c) Shankar Hemmady
d) Gabe Moretti
7 – SystemVerilog was donated to Accellera in _____.
a) 2000
b) 2001
c) 2002
d) 2003
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Tags: Aart de Geus, Accellera, Andrew Piziali, Brett Cline, Brian Bailey, Cadence, Cliff Cummings, CPF, DVCon, Gabe Moretti, Gary Smith, Grant Martin, IEEE Standards, JL Gray, John Cooley, Karen Bartleson, Kathryn Kranen, Magma, Mentor, MP Associates, OSCI, OVI, OVM, Paul McLellan, Rajeev Madhavan, Richard Goering, Synopsys, SystemC, SystemVerilog, Ted Vucurevich, UPF, UVM, Verilab, Verilog, VHDL, VHDL International, Wally Rhines
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