Posts Tagged ‘Xilinx’
Thursday, September 21st, 2017
Silicon Valley based Blue Pearl Software is the quintessential EDA company: privately held, run by a seasoned team of EDA experts, and with a portfolio that includes tools for generating timing constraints, CDC analysis, both synchronous and asynchronous, RTL verification tools for methodology standards and design rules, and design management tools.
Similarly, Blue Pearl’s Ellis Smith is the quintessential CEO in EDA. Before founding his current company, Smith was CEO and President of Orora Design Technologies, CEO at TransEDA through that company’s IPO in 2000, and CEO at Exemplar Logic through its merger with Mentor Graphics in 1995. His experience also includes a stint as CEO at CrossCheck Technology, and years spent at Duet Technologies, CADAM, Versatec, Dictaphone, and 3M. Pretty much the whole history of the EDA industry in one CV.
It would be an excellent idea to sit down for a very long conversation with Ellis Smith to discuss his take on the history of this oh-so-interesting industry. Unfortunately, time was of the essence when I did get the chance to talk with him earlier this month, and the focus was principally on Blue Pearl.
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Tags: Altera, Blue Pearl Software, Cadence, ESD Alliance, Mentor, MicroSemi, Synopsys, Xilinx
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Thursday, June 1st, 2017
Master technologist John Sanguinetti has made major contributions to the EDA industry in the first decades of his career, and is now doing the same for the IP industry. After finishing his PhD at University of Michigan, Sanguinetti worked at DEC, Amdahl, Elxsi, Ardent Computer, and NeXT, was President at Chronologic, Modellogic, and CynApps, and was CTO at Forte Design.
In 1990 while still at NeXT, Sanguinetti became convinced he could write a better simulator than Cadence’s VerilogXL, so working nights and weekends for several months he wrote VCS. The potential of the tool inspired Sanguinetti and Peter Eichenberger to found Chronologic. They launched the product in late 1992, and sold the company to Viewlogic in late 1994. Synopsys acquired Viewlogic in 1997, and VCS has continued on there as a foundational element of the company’s verification strategy.
Currently Sanguinetti is serving as Chairman at Adapt-IP, but given his long and distinguished history with EDA, he agreed to opine this week on Grand Challenges in EDA. In the following conversation, he offers two Grand Challenges in EDA and two in Security, the latter being an issue of rapidly growing concern worldwide.
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Tags: AdaptIP, Cadence, Chronologic, CynApps, Forte Design, Grand Challenges in EDA, IoT, John Sanguinetti, Modellogic, NeXT, Peter Eichenberger, Synopsys, SystemC IDE, USB, VCS, ViewLogic, Xilinx
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Thursday, September 17th, 2015
This week, Synopsys announced its HAPS-80 FPGA-based prototyping systems, which the company says “delivers up to 100 MHz multi-FPGA performance and high-speed time-domain multiplexing technology.”
Johannes Stahl, Synopsys Director of Product Marketing for Prototyping, told me in a phone call related to the announcement that when it comes to physical prototyping, “things are breaking.” Which is why, per Stahl, Synopsys is fulfilling the dreams of its customer base with these new HAPS-80 systems, fully integrated systems that address the biggest problems in prototyping.
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Tags: FPGA-based prototyping, Hanneke Krekels, HAPS-80, Johannes Stahl, John Koeter, Synopsys, Xilinx
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Monday, February 16th, 2015
Lauro Rizzatti, formerly VP of Marketing at verification-centric EVE, thought he was going to move to Oregon last year and retire, but he was wrong. Instead he is busier than ever, hard at work both in the EDA tech sector and in the larger world of venture capital.
Lauro is consulting with Mentor Graphics to promote the company’s ever-expanding presence in the world of emulation, and he is also involved with the Oregon Angel Fund, a group of investors led by Eric Rosenfeld and former SpringSoft USA President Scott Sandler, also busy residents of Oregon.
Mentor is one of the top two emulation companies in the world, along with Cadence. Synopsys also has a foot in the door of that market thanks to their 2012 acquisition of EVE, which brings us back to Lauro. It was after his year spent at Synopsys following the acquisition that he ‘retired’ to Oregon. Clearly, however, it was a waste of his 30+ years of experience in verification to not have him continue contributing to the conversation around that technology, hence his consulting work at Mentor.
I had a chance to talk with Lauro about all of this in a recent phone call, a discussion in which he celebrated the green of Oregon while also gently chiding the endless rain that makes that lushness possible.
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Tags: Cadence, custom FPGAs, Emulation, Eric Rosenfeld, EVE, IBM, Lauro Rizzatti, Mentor Graphics, Oregon Angel Fund, Scott Sandler, SPICE, Synopsys, Xilinx
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Tuesday, September 9th, 2014
Open source EDA software has been of interest to many, albeit not all, for a number of years. The appeal is intuitive: price point, ability to modify code, ability to weigh in on the design and usability, and so on. The drawbacks are also intuitive: unstable code, insufficient and/or eccentric documentation, ebb and flow of volunteer developers, lack of long-term support for algorithms and code, inability to interact with customers at a detailed enough level to provide software that truly solves problems and supports design.
There are two other drawbacks as well. Open source software is difficult to monetize around and it’s the antithesis of all things proprietary. The EDA industry, however, is profoundly proprietary. End of story?
Surprisingly, no. If you google “Synopsys Open Source”, you’ll get a whole page of links with this intro: “The following open source software are included in one or more Synopsys FPGA software products. Each is a link to information and source code for the respective package. In addition, when required by the open source license agreement, source code or information on acquiring source code is also included with the software product.”
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Tags: Altera, FLOSS, Linus Torvalds, Open Source EDA, Software Freedom Conservancy, Steve Jobs, SWIG, Synopsys, Xilinx, zlib
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Thursday, September 5th, 2013
Herb Reiter, founder and president of eda2asic, has been in the semiconductor and EDA industry for 30+ years, including stints at Barcelona Design, Viewlogic, Synopsys, VLSI Technology, and National Semiconductor. In the last few years, Reiter’s work has focused on SOI, 2.5/3D ICs, and FinFET topics in semiconductor design and manufacturing. Straightforward enough, until you realize that these are significantly different ‘3D’ technologies, where ‘3D’ means different things to different people.
In a recent phone call, I asked Reiter to distinguish between what he calls the “three legs” of technology choices and to weigh in on which “leg” is most likely to succeed.
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Fully-depleted SOI …
Per Reiter, “The original technology was partially-depleted SOI, a fairly thin film of silicon on top of a thin insulating layer. IBM came up with the idea, because substrate capacitance was slowing their chips down. They realized if they put in the insulating layer, they wouldn’t have to worry about substrate capacitance, because the oxide layer would insulate things.
“The planar transistor gate cannot reach all of the electrons in an 80-nanometer channel, cannot fully control the flow, and causes what we called ‘body-effect’ and ‘kink-effect’ design challenges. That’s why partially-depleted SOI was not widely used. So fully-depleted silicon on insulator, FDSOI, was introduced. It only has about a 20-nanometer active film on top of the oxide layer. The gate is sitting on top of the active film and can control all of the electrons passing through the source/drain channel, which is why it’s called fully-depleted SOI.
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Tags: 2.5/3D ICs, AMD, Amkor, Chenming Hu, eda2asic, Elpida, FDSOI, finFET, Herb Reiter, Hybrid Memory Cube, Hynix, IBM, Intel, Micron, partially-depleted SOI, Samsung, SanDisk, Soitec, STMicro, Tezzaron, Toshiba, TSMC, Xilinx
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Thursday, April 4th, 2013
Let’s be honest about this. The reason the Electronic Design Process Symposium takes place every year in Monterey is because of the surf and sunshine. Otherwise, this conference would be so much more appropriately located in Silicon Valley.
Oh well, where’s the harm? Just hop into your favorite woodie, be it a hybrid or an EV, don’t forget the suncream, sandtoys, and surfboard, and head on down to Monterey Bay for two days of great talks, good food, and quiet-ish contemplation, with an emphasis on -ish. The 20th annual EDPS awaits.
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Tags: Adapt-IP, Alcatel-Lucent, Aparna Dey, ARM, Brandon Wang, Cadence, Camille Kokosaki, Dan Nenni, Docea Power, Don MacMillen, Dusan Petranovic, E-System Design, eda2asic, EDPS 2013, Frank Schirrmeister, Gary Smith, Gene Jakubowski, Gene Matter, Gregory Wright, Guy Bois, Herb Reiter, Intel, Ivo Bolsens, James Colgan, John Heilein, John Swan, Kiron Pai, Luigi Capodieci GlobalFoundries, Mentor Graphics, Michael McNamara, Micron, Mike Black, Namraj Nandra, Naresh Sehgal, Net App, Nimbic, Oracle, Raymond Leune, Rob Aitken, SemiWiki, Space Codesign, Srinivas Nori, Srinivasa Banna, Synopsys, Tom Dillinger, Tom Quan, TSMC, Xilinx, Xuropa
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Thursday, February 28th, 2013
Sometimes magic happens at panel discussions at technical conferences, and that was the case mid-day on Wednesday at DVCon in San Jose this week, where the conversation was lively, entertaining and informative on the pedestrian, albeit foundational, topic of “Best Practices in Verification Planning.”
Ironically, the hour-long conversation did not appear to be planned at all, but to be organic and spontaneous. The Cadence-sponsored lunch and panel discussion, moderated by Cadence’s John Brennan, included Verilab’s Jason Sprott, Cadence’s Mike Stellfox, ParadigmWorks’ Ambar Sarkar, Maxim’s Neyaz Khan, Oski Technology’s Vigyan Singhal, and Xilinx’ Meirav Nitzan. The panelists began with an overview of their experiences.
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Tags: Ambar Sarkar, Cadence, DVCon 2013, Jason Sprott, John Brennan, Maxim, Meirav Nitzan, Mike Stellfox, Neyaz Khan, Oski Technology, ParadigmWorks, Verification Planning, Verilab, Vigyan Singhal, Xilinx
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Thursday, December 6th, 2012
Shakeel Jeeawoody is VP of marketing at Blue Pearl. I enjoyed a long conversation with Shakeel at SAME Forum in France in October, and again at ARM TechCon in November. We completed the discussion by phone this week, starting with a brief profile of Blue Pearl and a discussion of FPGA versus ASIC design needs.
Per Jeeawoody, “Blue Pearl has been around since 2005, we’re located in Santa Clara, and our technology has all been developed in-house. Our underlying technology improves RTL analysis using symbolic simulation techniques and adapting them to our customers’ market requirements. We have competitors in the linting and clock-domain crossing [CDC] space, but not many that can generate SDC constraints and offer easy-to-use tools that run on Windows at an attractive price point to support FPGA designers.
“More FPGA designers today struggle with IP integration in their projects in the same way ASIC designers have in the past; if they don’t do the right level of analysis, there are reliability problems in the field. With that in mind, we focus on addressing emerging and major FPGA design issues – one we call Grey Cell Methodology, and we offer mode-based analysis to address issues associated with longest path analysis.
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Tags: Altera, ARM TechCon, Blue Pearl, DATE, DesignCon, Grey Cell Methodology, RTL Signoff for FPGAs, SAME, Shakeel Jeeawoody, SNUG, Synopsys, Synplicity, Xilinx
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Tuesday, May 8th, 2012
DAC looms!
 And never more so than on Tuesday — especially this year, June 5th, when you’re going to have to make some terrible decisions about what to miss, and what not to miss.
First there’s the opening session in the morning when a boatload of awards are handed out, followed by the 2012 keynote. The Exhibition Hall won’t open until these things wrap up, so other than company meetings or company special-product announcement breakfasts, you should be able to be in the main theater at Moscone from 8:30 to 10:00 am or so.
Of course, worst case scenario: The opening session at DAC is always video-taped, so you could watch it at a later date after it’s uploaded to the DAC website but that’s hardly ideal.
This year’s main address will be delivered by ARM’s Mike Muller, “comparing the original ARM design of 1985 to those of today’s latest microprocessors … how far design has come and what EDA has contributed to enabling … systems, hardware, operating systems, and applications.” Then Muller plans to talk about 2020, how to get there, and what it will be like when we do. Conclusion? This stuff’s better heard in person than tape delayed. Go to the opening session, and plan not to regret it.
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Tags: ACM, Applied Micro, ARM, Atrenta, Brian Fuller, Cadence, CEDA, Chevy Volt, Cisco, DAC, Design Automation Conference, IPL Alliance, Jim Hogan, Jim Solomon, LSI, Mark Horowitz, McKormick & Kuletos', Mike Muller, PMC-Sierra, Realtek, STMicro, Synopsys, Xilinx, Yervant Zorian
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