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Posts Tagged ‘ARM TechCon’

Fall Schedule: Let the games begin

Thursday, August 28th, 2014

 

With the advent of September, the fall conference season begins. Here are some upcoming meetings you may want to attend.

* DesignCon China – September 2-5 – Shenzhen
Last year close to 13,000 attended ICC-China. Expect even more to attend this year.

* Mentor Graphics Forum – September 3 & 5 – Shanghai & Beijing
Keynote will be given by Mentor CEO Dr. Wally Rhines, followed by President of ARM Greater China Allen Wu talking about the next 10 billion chips to be manufactured in China.

* IDF14: Intel Developers Forum – September 9-11 – San Francisco
Intel CEO Brain Krzanich will give opening keynote, followed by lots of talk about the IoT.

* PCB West 2014 – September 9-11 – Santa Clara
The most important conference of the year for board designers.

* Mentor U2U Automotive – September 10 – Dearborn
The debut of a new Mentor User2User event focusing on one of Mentor’s favorite core competencies.

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Fall Calendar Update: The pace quickens

Thursday, September 5th, 2013

 

Okay, summer’s over, September has arrived, and it’s time to figure out where you’re going to go over the next few months, conference wise. Some events are imminent, but others are a ways out, giving you time to think about registering and attending. Some events are vendor neutral, while others are vendor specific, which doesn’t preclude a chance to learn stuff. Although this list is lengthy, it isn’t comprehensive.

* ITC 2013
International Test Conference
Anaheim – September 8-12

* IDF 2013
Intel Developers Forum
San Francisco – September 10-12

* SNUG Taiwan
Hsinchu – September 10-11

* CDNLive China 2013
Beijing – September 10

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Blue Pearl: Facilitating FPGA design

Thursday, December 6th, 2012

 

Shakeel Jeeawoody is VP of marketing at Blue Pearl. I enjoyed a long conversation with Shakeel at SAME Forum in France in October, and again at ARM TechCon in November. We completed the discussion by phone this week, starting with a brief profile of Blue Pearl and a discussion of FPGA versus ASIC design needs.

Per Jeeawoody, “Blue Pearl has been around since 2005, we’re located in Santa Clara, and our technology has all been developed in-house. Our underlying technology improves RTL analysis using symbolic simulation techniques and adapting them to our customers’ market requirements. We have competitors in the linting and clock-domain crossing [CDC] space, but not many that can generate SDC constraints and offer easy-to-use tools that run on Windows at an attractive price point to support FPGA designers.

“More FPGA designers today struggle with IP integration in their projects in the same way ASIC designers have in the past; if they don’t do the right level of analysis, there are reliability problems in the field. With that in mind, we focus on addressing emerging and major FPGA design issues – one we call Grey Cell Methodology, and we offer mode-based analysis to address issues associated with longest path analysis.

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Verific: SystemVerilog & VHDL Parsers



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