Open side-bar Menu
 What Would Joe Do?
Peggy Aycinena
Peggy Aycinena
Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at She can be reached at peggy at aycinena dot com.

EDPS 2013: surf, sand, serenity, semiconductors

April 4th, 2013 by Peggy Aycinena

Let’s be honest about this. The reason the Electronic Design Process Symposium takes place every year in Monterey is because of the surf and sunshine. Otherwise, this conference would be so much more appropriately located in Silicon Valley.

Oh well, where’s the harm? Just hop into your favorite woodie, be it a hybrid or an EV, don’t forget the suncream, sandtoys, and surfboard, and head on down to Monterey Bay for two days of great talks, good food, and quiet-ish contemplation, with an emphasis on -ish. The 20th annual EDPS awaits.

Thursday, April 18th, starts with a keynote from Xilinx CTO Ivo Bolsens. Not surprisingly, he’s talking about the all-programmable SOC at the heart of the next generation of embedded systems. With that talk alone, your 2-hour road trip has been worth your while.

Next on Thursday comes an “ESL & Platform” session/panel organized by Gary Smith and moderated by Swan on Chips’ John Swan. Speakers include Space Codesign co.Founder & President Guy Bois, Cadence Senior Director Frank Schirrmeister, Alcatel-Lucent MTS Gregory Wright, Adapt-IP CEO Michael McNamara, and Docea Power Sr. Applications Manager Gene Matter.

If you’re not already on a first-name basis with at least one of these guys, now’s your chance. They’ll be at the front of the room, the venue’s small and personable, and I promise they’ll be ready to engage in Q&A on all topics du jour – system-level tools, IP, multi-core processing, emulation, embedded hardware/software co-development, and reconfigurable SoCs. And yes, it’s true: What these guys don’t know about this stuff, simply isn’t worth knowing.

But that’s only the morning of the first day of the two-day EDPS event. The afternoon showcases Synopsys Senior Director Navraj Nandra. If you missed his excellent tutorial at last month’s SNUG, here’s your chance to hear him expound even further on mixed-signal IP for finFETs.

Then Intel Tech Lead Kiron Pai is going to talk Data Management for IP reuse, Nimbic VP Don MacMillen is going to talk Cloud Classroom, Xuropa co.Founder & CEO James Colgan is going to talk Cloud Collaboration, be it public or private, Intel Software Architecture Manager Naresh Sehgal is going to talk Cloud Workload, and NetApp Manager Camille Kokozaki will take it from there.

Thursday afternoon wraps up with eda2asic President Herb Reiter orchestrating an entire session on 3D-IC System Design. His speakers include Mentor Graphics TME Dusan Petranovic talking Verification and Extraction, Cadence Director Brandon Wang talking Holistic Approaches, Micron Tech Strategist Mike Black talking Hybrid Memory Cube, and E-System Design CEO Gene Jakubowski batting cleanup.

At this point, the sun will be settling down over the Pacific, the evening meal will be served, and Gary Smith will offer after-dinner comments on “Silicon Platforms + Virtual Platforms = An explosion in SoC Design.” Although seemingly algorithmic and agitating, the zen of the nearby Pacific will undoubtedly bring out the contemplative rather than the combustible in Smith’s topic.

Next morning, and on to Day Two at EDPS, SemiWiki Founder Dan Nenni will keynote on the finFET value proposition. Following on that theme, Cadence Sr. Tech Marketing Manager Aparna Dey will then lead an interactive session on finFET design, speakers to include Oracle CAD Tech Manager Tom Dillinger, TSMC OIP Marketing Director Tom Quan, ARM Fellow Rob Aitken, and Synopsys VP Raymond Leung.

FinFETs continue in the limelight with Dan Nenni’s session on foundry design enablement, which includes GlobalFoundries Fellow Srinivasa Banna, GF Director & Fellow Luigi Capodieci, GF Director Srinivas Nori, and ARM VP John Heilein. These folks will lay out the challenges ahead and simultaneously offer an opportunity for compare & contrast vis-a-vis TSMC’s Tom Quan commentary from earlier in the day.

Finally, as EDPS draws to a close on Friday, April 19th, Intel Software Architecture Manager Naresh Sehgal will wrap up the conference, followed by closing comments from Conference Chair John Swan.

Okay, I ask you: Does it get any better than this?

The sun will still be up, the Pacific will be just steps away from the edge of the Monterey Beach Resort where you’ve been holed up for two days, it will be Friday evening and you’ll be within walking distance of countless casual eateries lining the beach where all manner of food and drink can help ease your journey into the weekend.

Surf, sand, scenery, serenity, and semiconductors.

Does it get any better than this?


Related posts:

Tags: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,

Leave a Reply

Your email address will not be published. Required fields are marked *


DownStream: Solutions for Post Processing PCB Designs
TrueCircuits: IoTPLL

Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
TechJobsCafe - Technical Jobs and Resumes EDACafe - Electronic Design Automation GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise