Archive for the ‘Knowledge Depot’ Category
Monday, October 2nd, 2017
Accellera has just extended the review period for the Portable Stimulus Standard. The committee is now seeking comments up until the end of October. Breker would like to join the committee and say how important it is for users to get involved with this standard. While we, as vendors, have some experience in this area, we are not doing this day in and day out. We need your guidance and feedback.
Breker applauds Mark Glasser, principal engineer for NVIDIA, for being a user who is spending the time and effort to understand the emerging Portable Stimulus Standard (PSS). The points he raised in his recent blog are shared by a number of other users in the industry. His passion comes from the fact that he sees the potential of the work that is being undertaken and the impact that it could have on the verification community and the entire system development flow.
Users are, by definition, those in the trenches experiencing the problems and trying to find solutions. Within that community, there are only a few that can see beyond the current design and can look towards the future. Of those, only a precious few can help to influence the direction of the future. If you are one of those, then we ask you to get involved. Sitting on a standards committee can be tough and often dirty work, but there is no better way to guide the future direction of the industry.
We share Mark’s feelings that we should leverage the extensive expertise that exists in the language design community. It has taken many hundreds of man years of effort to get C++ to where it is today and we have seen, during our interactions with users, the power and flexibility that C++ provides to this problem.
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Tags: acceleera, Breker Verification Systems, DSL, early adopter release, Mark Glasser, NVIDIA, Portable Stimulus Standard, PSS/ C++, PSS/ DSL, SystemVerilog, uvm
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Wednesday, September 13th, 2017
When people talk about the Portable Stimulus Standard (“PSS”) they throw around the term “graph based” as if that somehow clarifies everything. They usually don’t bother to describe what it means, beyond it being some simple mathematical model. Some vendors even confuse it with the term “graphical”. To simplify this confusion, for this blog we will use the term “visual”. This blog will answer questions about how PSS relates to graphs and how those graphs relate to other similar graph-based models already used within the industry. (more…)
Tags: Breker, C++, DSL, graph-based, graphical representation, Petri nets, Portable Stimulus Standard, PSS, test map, TutorialsPoint, UART, UML Activity Diagrams, visual
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Monday, May 22nd, 2017
The creation of the Portable Stimulus standard has raised a number of issues about the tradeoffs between using an industry standard language and a domain-specific language. Several blogs have tried to make the case for one or the other and often use scare tactics to make one look better than the other. That is not the objective of this blog. Instead, it’s meant to provide some information as to why the inclusion of the C++ variant is a good thing for the industry. (more…)
Tags: Breker, C++, industry standard language, portable stimulus, PSS language, SystemVerilog, two-language solution, user community, uvm
2 Comments »
Tuesday, April 4th, 2017
When people think about design languages, they may not realize that the language is almost irrelevant. The language supports the underlying semantic model and it is this model that is important. EDA has defined design models at the gate level, the register transfer level (RTL) and various forms of behavioral levels. When we talk about RTL, we think about Verilog and VHDL, but they are only the languages that support that model, or very minor variations of it. But what about verification? (more…)
Tags: Accellera, Breker, graphs, Language Agnostic, portable stimulus, SystemVerilog, Vera, Verification Model, Verilog, VHDL
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Friday, March 17th, 2017
At the recent DVCon, I had the pleasure to moderate a panel that enabled users to talk about their experiences working with the Accellera standard’s body during the creation of the Portable Stimulus standard. I would like to thank Accellera for enabling such a panel and to Nanette Collins for organizing the panel and making sure that I had the easiest role in the ensuing discussion. I am sure that full write-ups of the panel will emerge, but I wanted to make the voice of the users heard. (more…)
Tags: Accellera, Analog Devices, Cavium, EDA, IBM, market leader, NVIDIA, portable stimulus, Portable Stimulus Working Group, Qualcomm, Users, verification
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Thursday, December 8th, 2016
In the movies, when a person acts irrationally they are usually declared to be mad and quickly placed in a straitjacket for the protection of themselves and those around them. If we continue those thoughts into the world of verification, SystemVerilog must be declared to be a mad language. (more…)
Tags: Accellera, Breker, coverage, graph-based, path constraints, performance, portable stimuls, Portable Stimulus Standard, power consumption, resource limitations, stress tests, SystemVerilog
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Friday, November 4th, 2016
Why is Accellera supporting the use of an industry standard language in the development of the Portable Stimulus Standard? (more…)
Tags: Accellera, Breker, C++, emulation, path constraints, portable stimulus, Results Checking, scenario model, Self-checking test scenario, SystemC, Verilog, VHDL, virtual prototype
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Thursday, September 29th, 2016
There is an important standard being worked on within Accellera and given its name, you might think that this is another incremental standard on a somewhat tired theme. It is called Portable Stimulus and yet it has almost nothing to do with stimulus and that stimulus, once generated by a tool not defined in the standard, is most certainly not portable. It is a fundamentally new approach to verification that could transform how chips and low-level software are verified. We will get back to the name in a moment, but the important thing is that users become informed about this new language and choose to have their voices heard in the standardization effort.
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Tags: acceleration, Accellera, Breker, EDA, functional verification, graph-based, portable stimulus, scenario model, SoC verification, testbench, Universal Verification Methodology, uvm
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Thursday, September 8th, 2016
As regular readers know, the Portable Stimulus Working Group (PSWG) of the Accellera System Initiative has been working for some time to develop a new way to define verification intent once and to be able to reuse that across all stages of the verification flow and to be able to reuse it across designs. This will dramatically increase verification efficiency and establish verification methodologies that are likely to be used for the next couple of decades. (more…)
Tags: Accellera, Breker, EDA, functional verification, IBM, NVIDIA, portability, portable stimulus, portable stimulus market leader, PSWG, reuse, SoC verification, software-driven verification, test generation, user advocate, verification efficiency, verification IP, verification methodology
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