The industry is excited about RISC-V, and rightly so. It is enabling companies to take back control of their software execution environment without having to assume the huge responsibilities that come along with processor development and support of an ecosystem for it. Maybe a company wants to use a commercially developed core today, get the software developed and the processor integrated and then in a future generation, replace that with their own core. Perhaps they envision a range of products where the processor is tuned for each product in the family. There are so many possibilities that were out of reach in the past. (more…)
The Breker Trekker
Posts Tagged ‘coverage’
PSS and RISC-V – A Match Made In Verification
Thursday, November 14th, 2019Portable Stimulus: Finding The Killer App
Thursday, November 29th, 2018Functional verification vendors have been talking a lot about the Portable Stimulus Standard (PSS), but what is it and why should you care? To put it in stark terms – because it is the first language that supports verification methodology and because the existing methodology is failing to provide the capabilities required for system-level verification. (more…)
Constrain Me, Please
Thursday, December 8th, 2016In the movies, when a person acts irrationally they are usually declared to be mad and quickly placed in a straitjacket for the protection of themselves and those around them. If we continue those thoughts into the world of verification, SystemVerilog must be declared to be a mad language. (more…)
Hitting the Town with DVClub
Thursday, September 1st, 2016For those unfamiliar with the idiom, “hitting the town” or “going out on the town” means heading out to make the rounds of bars, restaurants, theaters, clubs, etc. It’s usually used in a city where such entertainment options abound. The topic of today’s post on The Breker Trekker blog is a particular club, DVClub, that packs in plenty of solid technical information along with entertainment. You may not have to go far to hit one; a DVClub event is likely to be coming to your city soon.
The history of the Design Verification Club (DVClub) is quite interesting, stretching back more than ten years. It started as an informal event for verification engineers to get together to share stories and talk about new technologies to help them do their jobs. You might have noticed that, unlike DVCon, the title means “design verification” and not “design and verification.” This gathering is intended for semiconductor functional verification engineers.
A Further Preview of DVCon India 2016
Wednesday, August 24th, 2016Three weeks ago, we published a post on The Breker Trekker blog that previewed some of the talks and tutorials on the technical program at the upcoming third Design and Verification Conference and Exhibition (DVCon) India on September 15-16 in Bangalore. More of the details on the conference are now available online, and for today we’d like to highlight some of the keynote addresses, panels, and poster sessions on the agenda that also stand out for us.
As always, the program and steering committees have put a lot of thought into keynote speakers who will take a wide view of not just the EDA industry, but the larger electronics industry that we serve. Mentor CEO Wally Rhines is always a great speaker who comes armed with lots of charts and statistics to support his positions. His talk on “Design Verification: Challenging Yesterday, Today and Tomorrow” will survey the history and evolution of verification while predicting some of the future challenges
Why Portable Stimulus Must Be Bidirectional
Thursday, August 18th, 2016When we first began offering our Trek family of products for what’s now known as portable stimulus, we talked a lot about vertical and horizontal reuse. Vertical reuse means that you can create a scenario model for individual IP blocks and generate test cases to run in their UVM testbenches, then move up to clusters and subsystems. The IP models can simply be plugged together to form a higher-level model from which appropriate higher-level test cases can be generated.
At the full-SoC level, you can generate C test cases that run on your embedded processors. Horizontal reuse is the ability to move from simulation to hardware (acceleration/emulation, FPGA prototypes, and silicon) while generating appropriate tests for these platforms from the same SoC scenario model. We generally described both forms of reuse in a unidirectional flow. However, bidirectionality is very valuable and, we believe, essential for portable stimulus. Let’s cover that topic in today’s blog post.
DVCon India Just Keeps Getting Better
Wednesday, August 3rd, 2016As many of you know, in 2014 the longstanding Design and Verification Conference and Exhibition (DVCon) expanded beyond Silicon Valley to India. The first year of DVCon India was very successful for a new event, drawing more than 450 attendees from more than 80 companies and universities. Last year’s show grew to more than 600 engineers attending the technical program, visiting the vendor exhibition, and enjoying the numerous opportunities to network with their peers.
The third annual DVCon India will be held on September 15 and 16, once again at the Leela Palace in Bangalore. From our perspective, the show just keeps getting better and better every year. The full program is now available online, and for today’s post we’d like to mention some of the technical sessions that we think look especially interesting. In a future post, we’ll discuss other aspects of the program, including the keynote addresses.
Guest Post: More on EDA Startups, Behemoths, Corner Stores, and Zombies
Wednesday, July 27th, 2016Three weeks ago on The Breker Trekker, we published a post on “The Return of EDA Startups, Behemoths, Corner Stores, and Zombies” and saw a nice uptick in viewing. Zombies are always popular with our audience. Our post prompted some interesting observations from today’s guest blogger, Excellicon’s Sales and Operations VP Rick Eram. He has some thoughts on this way of dividing the EDA industry and suggestions on how customers should treat the different players:
The concept of corner stores is interesting since they pave the way for development and deployment of newer analysis and implementation technologies addressing today’s design challenges that are either not addressed by majors, involve much manual work despite available products, or are addressed by products that create a huge amount of data without means for interpretation. The startups develop new technologies and, while deploying their technology on their way to becoming corner stores, they master ways to deploy such new technologies. What differentiates corner stores from zombies is the deployment of the technology. These companies are the engines of innovation in today’s EDA industry and help the behemoths to cover the gaps in their traditional technologies after the newer technology catches on and adds value for customers.
Guest Post: Open Source Requires Open Minds, Especially in EDA Verification
Wednesday, July 20th, 2016Few recent announcements in the EDA, IP, or semiconductor industries have had the impact of SoftBank’s proposed US$32B acquisition of ARM. Many commentators have weighed in on this news. Today’s guest blogger, OneSpin Solutions Vice President of Marketing David Kelf, shares some thoughts on how changes to the ARM universe might intersect with ongoing changes in the open source community:
One side effect of the ARM acquisition news was an increase in the debate on the fascinating RISC-V Open Source processor development. Clearly this has the interest of a number of significant ARM users, judging by the recent workshop at MIT last week as one example, and might represent a significant game changer. It also begs the question on the application of Open Source, and indeed standardization efforts in general, in verification and how programs in this area might change the dynamics of increasingly closed environments from the two largest EDA vendors. (more…)
Evolution or Revolution in System-Level Verification?
Thursday, July 14th, 2016Recently, SemiconductorEngineering published the three–part series “System-Level Verification Tackles New Role” as part of its ongoing “Experts at the Table” discussions. The format is simple–an editor sits down with four or five industry experts to discuss a particular topic–but the debate can be lively and the result educational. Breker participates in these roundtables as often as we can, focusing of course on verification among the many technical topics covered by the site.
In advertising a “new role” for system-level verification, this particular series was not overstating the case. We tend to talk a lot about the evolution of verification in general, especially for system-on-chip (SoC) devices and multi-SoC systems. But in some ways what is happening now with our products and the Accellera portable stimulus standardization effort is more revolutionary than evolutionary. So which is it? We’ll attempt to answer that question in today’s post here on The Breker Trekker blog.
