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Tom Anderson, VP of Marketing
Tom Anderson, VP of Marketing
Tom Anderson is vice president of Marketing for Breker Verification Systems. He previously served as Product Management Group Director for Advanced Verification Solutions at Cadence, Technical Marketing Director in the Verification Group at Synopsys and Vice President of Applications Engineering at … More »

DVCon India Just Keeps Getting Better

August 3rd, 2016 by Tom Anderson, VP of Marketing

As many of you know, in 2014 the longstanding Design and Verification Conference and Exhibition (DVCon) expanded beyond Silicon Valley to India. The first year of DVCon India was very successful for a new event, drawing more than 450 attendees from more than 80 companies and universities. Last year’s show grew to more than 600 engineers attending the technical program, visiting the vendor exhibition, and enjoying the numerous opportunities to network with their peers.

The third annual DVCon India will be held on September 15 and 16, once again at the Leela Palace in Bangalore. From our perspective, the show just keeps getting better and better every year. The full program is now available online, and for today’s post we’d like to mention some of the technical sessions that we think look especially interesting. In a future post, we’ll discuss other aspects of the program, including the keynote addresses.

Of course, Breker will be exhibiting at the show, but we will also be speaking in the “How Portable Stimulus Addresses Key Verification, Test Reuse, and Portability Challenges” tutorial on Thursday. Organized by Accellera, it will provide an update on the activities within the Portable Stimulus Working Group (PSWG). Our CEO Adnan Hamid will show how portable stimulus enables test generation across the full range of verification platforms, from simulation to silicon.

Portable stimulus complements the widely used Universal Verification Methodology (UVM), and two tutorials cover UVM-related verification topics. Other tutorials in the Thursday program cover high-level synthesis, low-power design and verification, emulation, ensuring design quality, and verifying Internet-of-things (IoT) devices. We tend to focus on the verification aspects of DVCon, but it’s about design as well so it’s nice to see such a good mix of topics being addressed.

On Friday, the program turns toward technical papers and posters. The electronic system level (ESL) track tackles many aspects of system design and verification, including architectural exploration, low power techniques, and software/hardware co-design and co-verification. With self-driving cars so much in the news, a talk by Infineon on “Enabling Verification of Automotive Safety Application using Fault Injection in VP” sounds both timely and important.

Accurate pre-silicon performance estimation is one of the touted benefits for ESL, and so NXP’s talk on “Accurate and Flexible Traffic Simulation of Networking Use-cases for SoC Performance Analysis” is likely to be illuminating. NXP also discusses porting stimulus from UVM to C++ and virtual platform development. Other ESL topics coveted by papers and presentations include IP connectivity, the SystemC version of UVM, the UPF3.0 power format standard, and integration with IP-XACT.

There are even more papers in the design and verification (DV) track, so many of interest that it may be hard for one person to plan out the two days. Nine talks cover topics related to UVM and SystemVerilog, and that’s just the beginning. Other areas addressed in the technical program include acceleration and emulation, analog/mixed-signal (AMS) verification (including the use of UVM), formal analysis and assertions, and multiple aspects of low-power design and verification.

Two papers co-authored by Intel and Graphene Semiconductor sound very interesting: “Statically Dynamic or Dynamically Static? Exploring the power of classes in SystemVerilog Assertions for re-usability and scalability” and “Not Just one, 3 Ways to bring down the simulation turnaround time for SoC level assertion qualification.” Synopsys will present “Reusing System C traffic generators and tests in System Verilog for faster verification with UVM TLM 2.0” which sounds rather complementary to one of the NXP talks.

Although it doesn’t use the term, Broadcom’s title “UVM based SoC Verification Methodology to enable vertical/horizontal reuse across RTL integration hierarchies and workstation RTL simulations to emulation to post silicon” seems to fit within the general concept of portable stimulus. We’re also intrigued by the topic “Intelligent TestBench based on Load Distribution” to be presented by Analog Devices.

Mind you, these are just some of the titles in the technical program that caught our eye. There are many more and, whatever your interest in design and verification, you will be sure to find some talks of interest. Please take a few minutes to peruse the program and start to plan your time at the conference. Feel free to comment if you want to highlight particular tutorials or talks. Thanks, and we will see you soon at DVCon India.

Tom Anderson

The truth is out there … sometimes it’s in a blog.

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