It is unfortunate that design and verification methodologies have often been out of sync with each other, and increasingly so over the past 20 years. The design methodology change that caused one particular divergence was the introduction of design Intellectual Property (IP). IP meant that systems were no longer designed and built in a pseudo top-down manner, but contemplated at a higher level and constructed in a bottom up, ‘lego-like’ manner by choosing appropriate blocks that could implement the necessary functions. (more…)
The Breker Trekker
Posts Tagged ‘SystemVerilog’
Methodology Convergence
Thursday, August 8th, 2019Multi-Dimensional Verification
Tuesday, May 28th, 2019It seems like ancient history now, but in the not so distant past, verification was performed by one tool – simulation; at one point in the flow – completion of RTL; using one language and methodology – SystemVerilog and UVM. That changed when designs continued to get larger and simulators stopped getting fast enough. Additional help became necessary in the form of emulators and formal verification, but that coincided with an increasingly difficult task of creating a stable testbench. It was no longer possible to migrate a design from a simulator to an emulator without doing a considerable amount of work on the testbench. (more…)
Beyond Portable Stimulus 1.0
Thursday, August 23rd, 2018With the release of the 1.0 version of the Portable Stimulus Standard (PSS), the industry now has a solid base on which to build solutions and to ensure that the time and investment made by users to create verification intent models is portable. This should allow them to assess tools and decide which one fits their requirements best and which ones will fulfill their roadmap into the future. Unfortunately, it is not quite as easy as that, because many users have already moved beyond the basics as represented in the standard. (more…)
Industry Struggles with System Coverage
Thursday, March 15th, 2018DVCon is a great place to talk to design and verification engineers. As the Accellera Portable Stimulus Standard (PSS) gets closer to reality, we were able to share with them during the conference the progress made and the ways in which it may impact their task. Most of them are as excited about PSS as we are. While we have been working in this field for more than a decade and have received a lot of feedback, there are now many more people becoming aware of it and the potential that it has. This provides us with the opportunity to learn as well. (more…)
UVM is Dead! Long live UVM+PS!
Thursday, February 22nd, 2018When the forebears of SystemVerilog and UVM were being created, the world was a different place. Verification was primarily directed testing and code coverage was good enough to signal completion. Development of directed tests was getting to be slow, cumbersome and difficult to maintain. Languages and tools were created that added the ability to randomize stimulus but that created two problems. First, you had no idea what a test had accomplished and second, you had no idea that the design had actually reacted in the right manner. Thus, two additional models became necessary: a combination of checkers and scoreboard and the coverage model. The big problem was, and remains, that the three models are independent models only unified by a thin layer of syntax. (more…)
Dual Focus Will Help Adoption
Wednesday, January 31st, 2018One of the great things associated with the development of a standard, such as the Portable Stimulus Standard (PSS), is that it brings together various stakeholders – often a broader selection of people than any single company did business with. When you initially develop a product you gear it toward a particular problem, one that you have some familiarity with. The resulting product attracts engineers who resonate with the product and they provide valuable feedback. This in turn helps to make the product more attractive to engineers with a similar need. If you are not careful, you can have a product that targets a narrow part of the market and that is all you learn to explore. It is the Innovators Dilemma, and can stop a company from developing a general purpose product. (more…)
Solution = Standard + Tool
Thursday, November 30th, 2017Solutions are what users need and the existence of a standard gives them the assurance that models they create will be portable between tools. Put another way, the standard creates a level playing field on which vendors can create tools that provide solutions. (more…)
Time To Be Heard
Monday, October 2nd, 2017Accellera has just extended the review period for the Portable Stimulus Standard. The committee is now seeking comments up until the end of October. Breker would like to join the committee and say how important it is for users to get involved with this standard. While we, as vendors, have some experience in this area, we are not doing this day in and day out. We need your guidance and feedback.
Breker applauds Mark Glasser, principal engineer for NVIDIA, for being a user who is spending the time and effort to understand the emerging Portable Stimulus Standard (PSS). The points he raised in his recent blog are shared by a number of other users in the industry. His passion comes from the fact that he sees the potential of the work that is being undertaken and the impact that it could have on the verification community and the entire system development flow.
Users are, by definition, those in the trenches experiencing the problems and trying to find solutions. Within that community, there are only a few that can see beyond the current design and can look towards the future. Of those, only a precious few can help to influence the direction of the future. If you are one of those, then we ask you to get involved. Sitting on a standards committee can be tough and often dirty work, but there is no better way to guide the future direction of the industry.
We share Mark’s feelings that we should leverage the extensive expertise that exists in the language design community. It has taken many hundreds of man years of effort to get C++ to where it is today and we have seen, during our interactions with users, the power and flexibility that C++ provides to this problem.
Total Value Of A Standard
Monday, May 22nd, 2017The creation of the Portable Stimulus standard has raised a number of issues about the tradeoffs between using an industry standard language and a domain-specific language. Several blogs have tried to make the case for one or the other and often use scare tactics to make one look better than the other. That is not the objective of this blog. Instead, it’s meant to provide some information as to why the inclusion of the C++ variant is a good thing for the industry. (more…)
Portable Stimulus – The First Verification Model
Tuesday, April 4th, 2017When people think about design languages, they may not realize that the language is almost irrelevant. The language supports the underlying semantic model and it is this model that is important. EDA has defined design models at the gate level, the register transfer level (RTL) and various forms of behavioral levels. When we talk about RTL, we think about Verilog and VHDL, but they are only the languages that support that model, or very minor variations of it. But what about verification? (more…)
