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Posts Tagged ‘Verilog’

Portable Stimulus – The First Verification Model

Tuesday, April 4th, 2017

When people think about design languages, they may not realize that the language is almost irrelevant. The language supports the underlying semantic model and it is this model that is important. EDA has defined design models at the gate level, the register transfer level (RTL) and various forms of behavioral levels. When we talk about RTL, we think about Verilog and VHDL, but they are only the languages that support that model, or very minor variations of it. But what about verification? (more…)

EDA Hates C++. Wait, What – Back Up!

Friday, November 4th, 2016

Why is Accellera supporting the use of an industry standard language in the development of the Portable Stimulus Standard? (more…)

Verification Needed to Take High-Level Synthesis Mainstream

Tuesday, December 2nd, 2014

This blog focuses mostly on verification, but from time to time we like to take a look at other aspects of the EDA industry. Today we’d like to discuss high-level synthesis (HLS), its progress and status, and what’s keeping it from beingĀ  a mainstream technology used for every chip design. It turns out that this topic has a lot to do with verification, so we’re not straying too far from our primary focus.

To start, let’s define what we mean by HLS in contrast to the mainstream technology of logic synthesis. Generating gates from a hardware description language (HDL) moved from a research problem to viable products around 1988. The ultimate winner among several promising companies was Synopsys, in part because they chose a register-transfer level (RTL) subset of the popular Verilog HDL as their input format. Their tools generated a gate-level netlist using the cells available in an ASIC vendor’s library.

(more…)

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