New tools, languages, or methodologies can be an improvement over existing ones, or they can be enablers for something different. The recently approved Accellera Portable Stimulus Standard (PSS) can be either or both. (more…)
The Breker Trekker
Posts Tagged ‘RTL’
Improve or Enable
Thursday, April 18th, 2019Rewriting Revolutionary History
Friday, June 9th, 2017The semiconductor design industry has always preferred evolution over revolution. There have been a few successful revolutions but most of the time revolution happens over time through evolutionary steps. (more…)
Verification Needed to Take High-Level Synthesis Mainstream
Tuesday, December 2nd, 2014This blog focuses mostly on verification, but from time to time we like to take a look at other aspects of the EDA industry. Today we’d like to discuss high-level synthesis (HLS), its progress and status, and what’s keeping it from being a mainstream technology used for every chip design. It turns out that this topic has a lot to do with verification, so we’re not straying too far from our primary focus.
To start, let’s define what we mean by HLS in contrast to the mainstream technology of logic synthesis. Generating gates from a hardware description language (HDL) moved from a research problem to viable products around 1988. The ultimate winner among several promising companies was Synopsys, in part because they chose a register-transfer level (RTL) subset of the popular Verilog HDL as their input format. Their tools generated a gate-level netlist using the cells available in an ASIC vendor’s library.
