The Tate Effect: Confidence in Flex Logix Team & Technology

Geoff Tate, founding CEO at Rambus, is busy – again. These days he’s leading the charge with a new FPGA-based enterprise that, per Tate, wants to be “the first to the party” – a party that’s all about providing FGPA-based IP to a market increasingly in need of these products.

When Tate and I spoke by phone recently, he offered the Flex Logix elevator pitch, and then focused on the company’s August press release.

“We are like the ARM of FPGA,” Tate said, and then laughed. “No, we are not expecting to be acquired by SoftBank anytime soon.”

“However, ARM was the first to successfully embed processors,” he said, “and at Flex Logic we are [doing that] with FPGAs.”

Asked about his background, Tate offered: “I used to be the processor vice president at AMD, and there I met a young guy through my VC contacts who told me he had a better way to build FPGAs.

“Together we talked to some chip companies and found interest in reconfigurable RTL blocks where the protocols can be subject to change even after the chip is soldered into the system.”

Given the pent-up demand for such things, Tate said, “The response to our product offering has been really good. I believe we have the possibility of being as big as the embedded processor market.”

“And certainly big enough to make our investors happy,” he added.

Again referencing his background: “I had been the founding CEO at Rambus back when there were only four people in the company, so I have been through this before.

“Clearly, there is a lot of customer interest in the Flex Logix technology, but in the early stages of something new like this, because hiccups can be so expensive, customers are cautious and conservative – and rightly so. Looking for early adopters who are [willing to work with us] is therefore critical.

“We proved our silicon a year ago, which triggered our first customer deal – it’s been under license for over a year – and now we are in the process of porting our technology with lead customers to another node.”

Addressing the recent Flex Logix press release, Tate said, “What we are announcing is [support for] the 40-nanometer new Ultra Low Power [40ULP] node from TSMC.

“We completed the design a couple of months ago, and now a chip is in the fab to prove the silicon. We will validate it to verify performance and power, and to establish that it meets all of the specs.”

“And which EDA vendors is Flex Logix using to do its work?” I asked.

Tate replied, “We use a combination of Cadence and Mentor Graphics for our physical chip design, Synopsys Synplify for the front end of our process, and our own custom software for the back half. Finally, we use Mentor test software to complete the design.”

“Your confidence.” I noted, “indicates the team has been working on a clear road map from the very beginning.”

Tate conquered, “Yes, although there have been some surprises in going from TSMC 28 nanometers to their 40-nanometer ultra low power node. But [this porting] means we have reacted to where there is the greatest customer traction.

“As a startup, it is extremely important to develop stuff that people will actually use. It’s also important to have customers help fine-tune the technology. Some want super-low power for battery life, while others just need low power.

“Our architecture is the same across process nodes, but it’s this fine tuning of power, performance and area – done at different nodes – that makes our working with leading customers [so valuable].

“The customers doing design at 40-nanometer ULP have a very different set of performance and power trade-offs than those working at 28 nanometers. The 40ULP people want a different set of options and much more control – and they want us to design our storage units [with a special emphasis] on sleep mode.”

“And, although we ourselves might have thought of some of the [modifications] they’ve suggested, it’s far more effective when working with great customers,” he added.

“And how does a young company like Flex Logix find those great customers?” I asked.

Tate chuckled, “We knock on a lot of doors. And my background in Silicon Valley helps as well. Our investors include Lux Capital and Eclipse Ventures. These guys also open doors for us.”

“But sometimes even great customers,” I said, “can carry a grudge on the NIH front, not invented here.”

“Actually,” Tate replied, “not in the [area of] embedded FPGAs. Almost nobody has chips with embedded FPGAs, so there are no internal organizations [within the customer] that we’re competing against.

“In a few places where people do have embedded FPGAs – once they’ve seen our architecture, they conclude that our design is way better than theirs, and our scalability is much better. [They see] they can work with us, save money, and get better end results.

“Again, it’s a question of finding a few customers. Today [we believe] less than 5 percent [of customers] understand embedded FPGAs. While the other 95 percent of them say, ‘Embedded FPGAs? What’s that?’

“For most customers, their problem is the need to reconfigure RTL blocks – and that’s how they think about it.”

“Do you personally have a background in the FPGA space?” I asked.

“Not really in the FGPA space,” he answered. “We are not competing with Xilinx or Altera, but we are using FPGA technology to enable our customers. Just like ARM-enabled smart phones that could not be made with discrete processors.

“And one of our board members, Pierre Lamond [Eclipse Ventures], co-founded National Semiconductor. He was chairman of the board at Cypress Semiconductor and Microchips, and on the board of Mellanox in Israel.

“Pierre has extensive semiconductor experience, yet says he’s not investing in any semiconductor deals now, because it too hard to make the financials work. If you build chips, you need to pay for the masks, you’ve got to carry inventory, and [deal with] expensive package design.

“Pierre is investing in us, however, because we are developing IP, not making chips. There’s a difference. The IP business model doesn’t need a lot of capital.

“What we are developing is a block that goes into the chip. We don’t have to be experts in anything in the semiconductor area, and we don’t have to pay for the 100 engineers [associated with all of that].”

Tate also noted that although he’s been asked to lead several startups in recent, it’s the technology and team at Flex Logix that’s compelled him to lead this one: “My co-founder, Cheng Wang, strikes me as smart and hardworking. He’s got the brains and I’ve got the business side. I kind of know if things are on the right track.”

“What about the basic stats for the company,” I asked. “Who? Where? When?”

Tate obliged: “We’re based in Mountain View, with low double digits employees. Our technology stems from the work that Cheng Wang did at UCLA, along with a couple of other guys – Professor Dan Markovic [headed the team].

“While Cheng was at UCLA, he [and his colleagues] did five different test chips with 1000 lookup-table FPGAs. Their last chip had 30,000 lookup tables, plus DSP acceleration.

“Cheng observed in designing these FPGA chips, that most of the area was in the programmable interconnect used to connect the logic blocks. They needed 80 percent for the programmable interconnect – traditionally connected in a mesh interconnect. Xilinx and Altera in the 1990s.

“But Cheng came up with a new interconnect structure, licensed to us by UCLA, with twice the density compared with traditional mesh. It also uses fewer metal layers, which is important for high-volume customers. That’s when he [started thinking], I could start an FPGA company with this.”

“If UCLA owns and licenses this technology, what’s to stop a nascent competitor from competing with Flex Logix using the same technology?” I asked.

Tate was quick to respond: “We are not starting from scratch – instead of being 20th to the party, we intend to be the first.

“Our customers have been very surprised that we could get to working silicon within a year after starting. But again, we are not starting from scratch.

“Instead, we are now tuning the technology for embedded FPGAs, which has required some architectural changes. Plus Cheng rewrote the software in a format that is much more robust for commercial use.”

“UCLA stands to win if you succeed?” I asked.

“Yes, they are the ones with the patents.” Tate said. “We pay UCLA some royalties, and some fees. But everyone wins if Flex Logic succeeds.

“There’s a belief that only optimists start companies, and we are all optimists here at Flex Logix. Two years ago, I would have spoken about all of this with more conditionals, but now the things we wanted to happen are definitely happening.”

His confidence prompted two queries: “Given your success at Rambus, do you believe lighting can strike twice? More importantly, are you enjoying yourself in all of this?”

Tate was unequivocal: “Yes and yes.”

“Look, I made a lot of money at Rambus. I’m not doing this for the money. Life is too short to do the things you don’t enjoy.”

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Copy Editor’s Note …

Thank you to Linley Gwennap of the Linley Group for kindly pointing out the subtle difference between affect and effect. His copy edit has been gratefully noted, and the change implemented in the title of this blog.

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Tags: AMD, ARM, Cadence, Cheng Wang, Cypress Semiconductor, Dan Markovic, Eclipse Ventures, eFPGA, Flex Logic, Geoff Tate, Lux Capital, Mellanox, Mentor Graphics, Microchips, National Semiconductor, Pierre Lamond, Rambus, reconfigurable RTL blocks, SoftBank, Synopsys, TSMC 40ULP, UCLA

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