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Peggy Aycinena
Peggy Aycinena
Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at www.aycinena.com. She can be reached at peggy at aycinena dot com.

Flex Logic & TSMC: embedded FPGA cores on 16nm FinFETs

 
December 14th, 2016 by Peggy Aycinena


Flex Logic announced some astonishing news this week
– the completed design of a “high-performance IP core for TSMC 16FF+ and 16FFC, with performance for wide, single-stage logic around ~1GHz at worst case PVT conditions.”

In a phone call to discuss the announcement, Flex Logic CEO and Co-founder Geoff Tate was clearly ebullient: “Last August we were talking about TSMC’s 40-nanometer ULP, ultra low power, and now this week we’re talking about the first 16-nanometer finFET plus.

“This one, our EFLX 100, is like the one we announced at 40 nanometers – but at 16 nanometers it will run much faster!

“We’ve done extensive measurements [to confirm] for many applications that these cores will run at 1GHz or faster, even in worst-case temperature conditions.”

“And they have been optimized,” Tate added, “for networking, base stations, and data center chips. This last is where we are seeing increasing demand, because these data center customers [have to deal with] chips that have problematic protocols.

“There are many protocols in the data center – for security, for storage, for networking – but the standards in these areas are changing, so data center customers have to swap out their chips from time to time [to keep up].

“Therefore these days, not surprisingly, data centers are asking for chips that can be reprogrammed – something that people have been already doing at the chip level.”

“For instance,” he said, “there are devices from Microsoft and Mellanox, companies which are already talking about programmable products.

“But we’ll see more programmability in the chip itself, now that embedded FPGAs provide this capability at a high-performance level and low-cost.”

“Re-programmability has always been intuitively pleasing and is now becoming a reality,” I said. “Why do we still need ASICs?”

“Not everything actually changes over time,” Tate responded, “and there is a cost associated with programmable logic – it take so much more space. The chips can be very big and some are actually huge.

“So it’s the chip company’s decision – use hardwired devices for [capabilities] that don’t need to adapt and use FPGAs for what does need to adapt and change. That is the best way to achieve the longest product life at the lowest cost.

“Today’s embedded FPGAs give customers the lowest cost chip they can get, with all the progammability they need.

“But the key point here is not how much programmability, but that the chips are becoming programmable at all – and that different companies will use different mixes of programmability using our solutions available at the finFET nodes.”

“Have you had a lot of cooperation from TSMC in all of this?” I asked.

“Yes,” Tate said, “they’ve been very helpful – at 40 nanometers, with early access to their 28-nanometer process, and a lot of cooperation at 16 nanometers. TSMC likes the idea of what we’re doing, because they think it’s a technology their customers should have access to.”

“Are you working with any other foundries?” I asked.

“You know,” Tate replied, “TSMC is the biggest foundry in the world by far, 5-to-6 times bigger than Number 2. We are responding to what most customers want, and most customers use TSMC.

“Someday there may be a customer who wants something else, but today the vast majority of customers want TSMC and so far, that’s been the right decision for us.”

“More importantly,” he emphasized, “we’re even seeing interest in our technology on some of TSMC’s earlier process nodes.

“I suspect in 2017 we’ll be offering our technology on these earlier nodes, because there is so much design going on right now for IoT devices on these older process nodes.”

“Overall, we are definitely see a lot of opportunity going forward!”


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Editor’s Note …

The validation chip for the EFLX-100 IP cores in TSMC 16FF+/FFC will soon be in fabrication, and expected to complete validation in early 2017.

However, the software for programming and checking timing performance is available now for TSMC 16FF+ EFLX-100 arrays. Flex Logix offers evaluation licenses at no cost so designers can check RTL performance and architecture ideas.


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Press Release …

December 13, 2016 – Flex Logic Technologies, Inc., the leading developer of embedded FPGA IP cores and software, today announced it has completed design of a high-performance IP core for TSMC 16FF+ and 16FFC, with performance for wide, single-stage logic around ~1GHz at worst case PVT conditions.

Expected to be fully validated in silicon in early 2017, the EFLX-100 embedded FPGA IP core for TSMC 16FF+ and 16FFC will enable customers to design their next-generation networking, base station and data center chips with reconfigurable RTL that can be quickly, easily and cost-effectively updated or changed at any time after fabrication, even in-system.

The EFLX-100 embedded FPGA core in TSMC 16FF+ and 16FFC has an architecture optimized for high speed control logic where hundreds of signals can be processed at speeds around 1GHz with single stage RTL logic, producing dozens of control signals. The EFLX-100 can be “arrayed” to build high speed control logic blocks from ~100 LUTs to ~3000 LUTs.

The 16nm version of EFLX-100 has two architectural changes and physical design optimatizations from the 40nm version:

* 224 inputs and 224 outputs: increased I/O enables wider control signal paths to be processed

* 6-input LUTs (which can also be dual 5-input LUTs): enables more processing to be done in a single stage for higher logic density and higher performance

* The power bus has been designed to be very robust to handle high switching activity at 1GHz+ at worst case PVT conditions.

* The core operates over the full range of voltages.

* The core requires only 5 routing layers of metal and is compatible with almost all metal stack-ups.

* An EFLX-100 IP core in TSMC 16FF+/FFC has an area of 0.05mm2.

Flex Logix has already begun design of the larger EFLX-2.5K embedded FPGA IP cores in TSMC 16FFC: both the all-logic and DSP versions, which are interchangeable to build arrays over 100K LUTs. These will be available in early 2017 and will be validated in silicon.

A TSMC 16FF+ version will also be available. The EFLX-2.5K enables large, fast array that can be used to implement accelerators for wireless base stations, networking and data center processor acceleration functions.

The design kit for the Customer’s requested EFLX Array includes GDS-II, LIB, LEF, Verilog model, CDL/Spice netlist, Test Vectors, Validation report, detailed Datasheet, Integration Guidelines & the EFLX Compiler.


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Validation Silicon in Fab …

Flex Logix proves out all of its IP cores in silicon for each major process node to ensure low risk of integration, even though its IP is all digital and compatible with logic DRC rules and the IP is simulated under worst case conditions: maximum frequency, high utilization and RTL with very high toggle rates to check for worst case static and dynamic IR drops.

Validation verifies in silicon that the recommended power grid architecture enables full speed operation at full utilization with high toggle rates under worst case conditions. The company checks enough array combinations to be sure that the inter-core array-interconnect is functional on all sides thus ensuring array reliability.

Flex Logix uses an on-chip PLL to test on-chip at frequencies of 1GHz+ and above to confirm all functional and performance operation over the full temperature and voltage range. Each EFLX array interconnects with external I/O for test and with on-chip SRAM for high speed pattern testing.

Each array has a process, voltage and temperature monitor to ensure precise control over testing at worst case conditions. Power domains are dedicated to each EFLX array and separately for SRAM and I/O and PLL so voltage range can be measured precisely for each IP. Once validation is complete, a detailed validation report will be available under NDA to interested customers.

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