Posts Tagged ‘NVIDIA’
Thursday, December 21st, 2017
Verific Design Automation in based in Alameda, not exactly Silicon Valley, but close enough to be within driving distance. The company has been in existence for almost 20 years and reports few competitors, if any. Instead, they see themselves as the de-facto standard for HDL language parsers, and as such can be found in just about every chip design flow.
In fact, according to Rick Carlson, Verific VP of Worldwide Sales, he’s more astonished with each passing day just how many places applications developed on top of Verific can be found. Not because he doubts the quality of the product, but because of the wide diversity of industries who are now developing chips.
Rick Carlson also knows a thing or two about building collegiality between the companies that constitute the EDA industry. He was one of the founders of the EDA Consortium 30 years ago, and the Phil Kaufman Award. We spoke at length last month.
(more…)
Tags: AI, Apple, Applicon, ARM, Atari, Averant, Cadence, Calma, Commodore, Computervision, Daisy Systems, Dave Millman, EDA Consortium, EDA Systems, EDAC, Escalade, ESD Alliance, Go, IEEE 1801, IIT Chicago, Intel, Invionics, Mentor, Microsoft, Northstar, NVIDIA, Phil Kaufman Award, Qualcomm, RISC-V, Samsung, Sinclair, Steve Jobs, Synopsys, Synplicity, UPF 3.0, Valid Logic, Verific
No Comments »
Thursday, September 28th, 2017
Vic Kulkarni is well-known in the EDA community as co-Founder, CEO and President of Sequence Design from 1995 until the company merged with Apache in 2009, which in turn was acquired by ANSYS in 2011. Kulkarni is now VP and Chief Strategist in the Office of CTO for the Semiconductor Business Unit at ANSYS.
There is little Kulkarni has not seen in his 30+ years in Silicon Valley. Although our conversation here mostly highlights current successes at ANSYS, it’s clear he continues to be wildly enthused about the broader promises of technology and the exciting efforts underway to create tools and strategies to bring those promises to fruition. Vik Kulkarni’s enthusiasm is the kind of thing that continues to make this industry so vibrant, and makes careers herein appealing for the next generation of engineers.
(more…)
Tags: Aart de Geus, Ansys, Apache, ARM, Bollywood, Cadence, DAC, ESD Alliance, John Lee, Lip-bu Tan, Mentor Graphics, Moore's Law, More than Moore, NVIDIA, Sequence Design, Synopsys, TSMC, Vik Kulkarni, Wally Rhines
No Comments »
Thursday, August 31st, 2017
Amit Gupta is the quintessential entrepreneur in EDA. Even as he was graduating with degrees in EE and CS from University of Saskatchewan, he was co-founding Analog Design Automation, targeted at those who need tools to automate analog chip design. That was in 1999. The company was sold to Synopsys in 2004, and then Gupta co-founded Solido Design Automation in 2005.
This week, I had a chance to speak at length with Amit Gupta. The last time we conversed, it was at the January 2017 Kaufman Award dinner for Dr. Andres Strojwas in San Jose. That evening, Gupta was enthused about Solido’s access to high-quality engineering talent in Canada, and argued that the cost of living and quality of life in Saskatoon, where Solido is headquartered, more than compensate for any sense that Silicon Valley is the epicenter of the industry. His enthusiasm has only grown since that time.
(more…)
Tags: Amit Gupta, Analog Design Automation, Deloitte, Design Automation Conference, E3 Data Science, Eric Hall, ESD Alliance, finFET, GlobalFoundries, Gloria Nichols, Jeff Dyck, Mark Gilbert, NVIDIA, Qualcomm, Samsung, Saskatoon, SOI, Solido Design Automation, Sorin Dobre, Synopsys, Ting Ku, TSMC, UX design
No Comments »
Wednesday, June 14th, 2017
The following transcript is from a panel that’s not showcasing at the Design Automation Conference next week in Austin. It was submitted as an idea last Fall, but was declined by conference organizers.
Why was that? Is the idea of crowd sourcing chip design a tad too open source-ish for the EDA establishment, too community based and innovative? Who knows.
The panel discussion took place, nonetheless, several weeks ago and is available below. It’s a conversation between eFabless Co-founder & CTO Mohamed Kassem and TopCoder Co-founder Jack Hughes, now Director of Tongal and member of the eFabless Board.
Per the eFabless website, the company “applies collective and multidisciplinary community knowledge to all aspects of semiconductor product development.”
Per the TopCoder website, this company has a “community of over 1,000,000 design and technology experts [providing] on-demand capability, bandwidth, and velocity so you can do more.”
The dialog below reflects both Jack Hughes’ and Mohamed Kassem’s deep knowledge around the issues of building design communities, open-source technology, and crowd sourcing design.
(more…)
Tags: Amazon, Apple, ARM, Crowd sourcing, DAC 2017, eFabless, Facebook, Fitbit, GitHub, Google, GoPro, Jack Hughes, Linux, mixed-domain knowledge, Mohamed Kassem, NVIDIA, RISC-V, Tongal, TopCoder, Wally Rhines, X-Fab
No Comments »
Thursday, May 12th, 2016
Aachen-based Silexica is making waves in the world of multi-core and embedded systems, as evidenced by their recent win in the German Silicon Valley Accelerator program. Company leadership was motivated to spend Q1_2016 in Silicon Valley, networking and meeting with thought leaders in the Bay Area’s tech community.
While he was in California, I had a chance to speak by phone Silexica CEO Max Odendahl. As many know, the problem of parsing code to take advantage of multi-core systems is a massively tough one to solve, one of the Grand Challenges in computing. My conversation with Odendahl was compelling, because it would appear his company has the solution.
(more…)
Tags: Altera, ARM, Cadence, Ericcson, German Silicon Valley Accelerator, Max Odendahl, Movidius, NVIDIA, NXP, RWTH Aachen University, Silexica, Synopsys, TI
No Comments »
Thursday, March 17th, 2016
Mentor Graphics’ Tom Fitzpatrick gave a lunchtime talk at DVCon several weeks ago summarizing recent efforts to build a standard [set of standards?] around portable stimulus for verification. The room was packed with over 200 people and his talk was sufficiently complete, nobody asked any questions.
After his presentation, however, I did hear some comments. Namely that these types of standards are quite complex and difficult to develop. Hence, setting an actual delivery date of January 2017 for Portable Stimulus Standard Version 1 [PSS V1] is quite aggressive and optimistic.
I was not fully informed about Accellera’s Portable Stimulus Working Group [PSWG] prior to Fitzpatrick’s talk, so could not judge whether January 2017 is or is not overly optimistic as a delivery date for the standard. Since DVCon, I have studied the slides and attempted to better understand what this is all about: What is a Portable stimulus and what would a set of standards look like?
(more…)
Tags: Accellera, Accellera PSWG, Agnisys, AMD, AMIQ EDA, Analog Devices, Breker Verification Systems, Cadence, Cisco, DVCon, Faris Khundakjie, IBM, Intel, Mentor Graphics, NVIDIA, NXP, Portable Stimulus Working Group, Qualcomm, Semifore, Synopsys, Tom Anderson, Tom Fitzpatrick, Vayavya Labs
1 Comment »
Thursday, November 5th, 2015
Since initiating their Decoding Formal Club in October 2013, Oski Technology has hosted this much-needed get-together every quarter, most recently on October 21st of this year at the Computer History Museum in Mountain View. I was fortunate to attend the debut meeting in 2013, so it was interesting to hear from Oski VP Jin Zhang that the support group is proving valuable to the growing numbers who attend.
“The first time we held the meeting,” Zhang said, “it was by invitation only, and we included about a dozen folks. Since that first event, we have continued to use the same room at the Computer History Museum, a room that can hold up to 40 people.
“The workshop, however, is continuing to grow very nicely, so we are faced with either finding a new venue or working with the museum to arrange for a bigger room for our next meeting in the first quarter of 2016.”
Zhang said interest in the event has increased to the point that people sign up to attend as soon as the date and time are announced. “They want to be sure they’ve got a spot,” she said.
(more…)
Tags: Apple, ARM, Broadcom, Cadence, Decoding Formal Club, formal verification, Google, Intel, Jin Zhang, Mentor Graphics, NVIDIA, Oski Technology, Synopsys
1 Comment »
Thursday, September 3rd, 2015
Alain Labat, the former President & CEO of VaST Systems, told me on a phone call this week that his story, in a way, is very simple: “When we got acquired by Synopsys in 2010, 5 years ago now, our management and investors clearly saw an opportunity to start our own investment bank and advisory company, so that’s what we did.
“We believed then, and still believe, that if you need a big bank from New York or a huge amount of money [to begin your enterprise], the right people are the Goldman Sachs or the other Wall Street guys. But for a technology-based company, you need something different.
“And so, at the advice of our investors, we started Harvest Management Partners specifically for those companies who need something different. Coming from VaST as we did, with a great deal of true operational experience, we felt we could offer much-needed guidance to those companies who were not a good fit for Wall Street.
(more…)
Tags: Alain Labat, Ansys, Bosch, Delphi, Docea Power, FCA Group, Fiat Chrysler Automobiles, Greg Hinkley, Harvest Management Partners, Intel, Jen-Hsun Huang, Kyle Park, Mentor Graphics, Nimbic, NVIDIA, Synopsys, Tanner EDA, Tesla, VaST Systems, Wally Rhines
1 Comment »
Thursday, September 26th, 2013
A Professor, a Sage, and a Guru walked into a bar. Brian the Bartender, greeted them: “What’ll it be, boys?”
The Professor said, “We need some help, Brian, settling an argument.”
“No problema,” Brian the Bartender said. “I’ve got an answer for everything.”
“Well,” the Professor said, “I think ESL’s not going to happen in our lifetime, but the Guru here says it’s just around the corner now that he and his have finally got all the pieces of the flow in place.”
Brian the Bartender laughed, “Yeah, the Guru’s been saying that since the dawn of mankind!”
“Exactly,” the Professor said.
Again Brian the Bartender laughed, “Guru, can you defend yourself? And don’t even think about plunking your wordy White Paper down on the bar. This is a public house, not a public library.”
(more…)
Tags: Apache, ARM, Atrenta, Cadence, Cadence System-to-Silicon Verification Summit, Calypto, DOCEA, Duolog, ESL, Forte, Green Hills, Imperas, Intel, Jasper, MathWorks, Mentor Graphics, NVIDIA, Oasys, OneSpin, Real Intent, Synopsys, Verification, Wind River
1 Comment »
Wednesday, September 12th, 2012
This is a great story: Oski Technology decided to prove the validity and efficiency of Formal Verification, and proposed a public challenge for themselves at DAC – a 72-hour window of time in San Francisco whereby they would attack a design problem never before seen, analyze it, propose a verification plan, and execute on that plan between 5 pm on DAC Sunday and 5 pm on DAC Wednesday.
To get a design problem, Oski Technology put out a request for proposal to different companies. The design could be at any stage in development, but had to include the RTL and some level of specifications for what the architecture should do, as well as some simulations.
Among the 5 respondents, Nvidia’s suggested problem was the most appropriate: It was a design that was still not complete and needed verification. More importantly, Nvidia was not afraid to have possible bugs or flaws in the design made public, a sign of their own confidence. So at 5 pm on Sunday, June 3rd, the Oski Technology team opened the files provided by Nvidia.
I’ll let Vigyan Singhal, Oski Technology’s President and CEO, take the story from there in his own words. Vigyan and I spoke by phone on September 12th, the same day a 6-minute video of the whole process was made available by the company. [Here’s the link on YouTube.]
**********************
The challenge …
 Per Vigyan Singhal: “We had gotten the design in advance from the verification manager at Nvidia, but couldn’t even look at the documentation until 5 pm on Sunday, let alone the RTL files. Then after we opened everything, we looked at the code and the design specifications and went from there.
“Initially during the first night and the next morning, we were mostly doing planning. As we learned more about the design, as is usual with this type of thing, we found some unexpected things. Some of the sub-modules were missing from the design. Nvidia had given us the simulation waves, however, so we could guess the functionality and from there wrote Verilog for those little modules.
(more…)
Tags: 72-hour Verification Challenge, DAC 2012, formal verification, NVIDIA, Oski Technology, Vigyan Singhal
No Comments »
|
