Posts Tagged ‘Altera’
Thursday, September 21st, 2017
Silicon Valley based Blue Pearl Software is the quintessential EDA company: privately held, run by a seasoned team of EDA experts, and with a portfolio that includes tools for generating timing constraints, CDC analysis, both synchronous and asynchronous, RTL verification tools for methodology standards and design rules, and design management tools.
Similarly, Blue Pearl’s Ellis Smith is the quintessential CEO in EDA. Before founding his current company, Smith was CEO and President of Orora Design Technologies, CEO at TransEDA through that company’s IPO in 2000, and CEO at Exemplar Logic through its merger with Mentor Graphics in 1995. His experience also includes a stint as CEO at CrossCheck Technology, and years spent at Duet Technologies, CADAM, Versatec, Dictaphone, and 3M. Pretty much the whole history of the EDA industry in one CV.
It would be an excellent idea to sit down for a very long conversation with Ellis Smith to discuss his take on the history of this oh-so-interesting industry. Unfortunately, time was of the essence when I did get the chance to talk with him earlier this month, and the focus was principally on Blue Pearl.
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Tags: Altera, Blue Pearl Software, Cadence, ESD Alliance, Mentor, MicroSemi, Synopsys, Xilinx
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Wednesday, July 19th, 2017
Impersas CEO Simon Davidmann lead a tutorial at the Design Automation Conference last month in Austin. Prior to his presentation, we spoke by phone about the content of that tutorial.
“It’s a simple message we’re presenting at DAC,” Davidmann said, “but an important one. If you’re a semiconductor guy building a chip, your customers want to know what components are being used, but you also have to build the software that runs on top of it.
“There’s a lot of challenge, however, in getting an operating system up and running on the hardware and the problem extends to hardware-dependent software. Even the lowest level bits become part of the operating systems. So our tutorial is about what you need to do this work, about how to get hardware-dependent software running.”
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Tags: Agile, Altera, Cadence, CloudBees, Design Automation Conference, Imagination Technologies, Imperas, Jenkins, Linux, Simon Davidmann, Synopsys
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Thursday, June 30th, 2016
Exuberance and Optimism: the only two words required to describe EDA-Careers’ Mark Gilbert – even after 20 years in the trenches sorting out the who what and where of just about everybody in the EDA industry. Yes, he self-identifies as the fun guy in the white suit, seen hither and yon wherever the EDA Nation chooses to confab, but in reality he’s the good guy in the white hat who’s going to tell it to you straight, about your career and your goals.
Also by his own description, Mark Gilbert is “the big fish in a little pond” who serves as the leading head hunter and career counselor extraordinaire of EDA.
I was lucky enough to speak with Gilbert by phone this week. As he and I were both on the East Coast, coordinating the hour of the call was easy. Our conversation started with the usual query: How did you get started in this business?
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Tags: Aart de Geus, Altera, ATopTech, Cadence, EDA, EDA-Careers, Mark Gilbert, Mentor Graphics, Synopsys, Wally Rhines
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Thursday, May 12th, 2016
Aachen-based Silexica is making waves in the world of multi-core and embedded systems, as evidenced by their recent win in the German Silicon Valley Accelerator program. Company leadership was motivated to spend Q1_2016 in Silicon Valley, networking and meeting with thought leaders in the Bay Area’s tech community.
While he was in California, I had a chance to speak by phone Silexica CEO Max Odendahl. As many know, the problem of parsing code to take advantage of multi-core systems is a massively tough one to solve, one of the Grand Challenges in computing. My conversation with Odendahl was compelling, because it would appear his company has the solution.
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Tags: Altera, ARM, Cadence, Ericcson, German Silicon Valley Accelerator, Max Odendahl, Movidius, NVIDIA, NXP, RWTH Aachen University, Silexica, Synopsys, TI
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Tuesday, September 9th, 2014
Open source EDA software has been of interest to many, albeit not all, for a number of years. The appeal is intuitive: price point, ability to modify code, ability to weigh in on the design and usability, and so on. The drawbacks are also intuitive: unstable code, insufficient and/or eccentric documentation, ebb and flow of volunteer developers, lack of long-term support for algorithms and code, inability to interact with customers at a detailed enough level to provide software that truly solves problems and supports design.
There are two other drawbacks as well. Open source software is difficult to monetize around and it’s the antithesis of all things proprietary. The EDA industry, however, is profoundly proprietary. End of story?
Surprisingly, no. If you google “Synopsys Open Source”, you’ll get a whole page of links with this intro: “The following open source software are included in one or more Synopsys FPGA software products. Each is a link to information and source code for the respective package. In addition, when required by the open source license agreement, source code or information on acquiring source code is also included with the software product.”
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Tags: Altera, FLOSS, Linus Torvalds, Open Source EDA, Software Freedom Conservancy, Steve Jobs, SWIG, Synopsys, Xilinx, zlib
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Thursday, December 6th, 2012
Shakeel Jeeawoody is VP of marketing at Blue Pearl. I enjoyed a long conversation with Shakeel at SAME Forum in France in October, and again at ARM TechCon in November. We completed the discussion by phone this week, starting with a brief profile of Blue Pearl and a discussion of FPGA versus ASIC design needs.
Per Jeeawoody, “Blue Pearl has been around since 2005, we’re located in Santa Clara, and our technology has all been developed in-house. Our underlying technology improves RTL analysis using symbolic simulation techniques and adapting them to our customers’ market requirements. We have competitors in the linting and clock-domain crossing [CDC] space, but not many that can generate SDC constraints and offer easy-to-use tools that run on Windows at an attractive price point to support FPGA designers.
“More FPGA designers today struggle with IP integration in their projects in the same way ASIC designers have in the past; if they don’t do the right level of analysis, there are reliability problems in the field. With that in mind, we focus on addressing emerging and major FPGA design issues – one we call Grey Cell Methodology, and we offer mode-based analysis to address issues associated with longest path analysis.
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Tags: Altera, ARM TechCon, Blue Pearl, DATE, DesignCon, Grey Cell Methodology, RTL Signoff for FPGAs, SAME, Shakeel Jeeawoody, SNUG, Synopsys, Synplicity, Xilinx
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Thursday, March 29th, 2012
Here are the Top Ten reasons to be going to EDPS next week in Monterey:
10) Next week’s a lighter work week for most and the Monterey Peninsula is beautiful at any time of the year, but particularly in the spring.
9) The Electronic Design Process Symposium is in its 19th year, and everybody who’s anybody in EDA and its adjacencies has attended at one point or another.
Eight) The topics discussed at EDPS have always tracked the trajectory of the industry. In 2000, those topics included: deep sub-micron, distributed and web-based design methodologies, designer productivity, and maintaining modularity in an integrated design flow.
Here in 2012, technology evolution has driven a completely different set of topics: embedded processors, FPGAs, ESL, NUMA, EDA in the Cloud, Big Data and the Big Servers that serve them, low-power design, and 3d-ICs, among others.
7) Going to conferences is as much about conversations outside the sessions, as it is about presenting or listening within the sessions. EDPS is a boutique conference, where I promise you’ll have a chance for substantive conversations with the speakers, both inside and outside of the sessions.
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Tags: 3D-ICs, Altera, Arif Rahman, Azadeh Davoodi, Cadence, Deepak Sekar, Don MacMillen, Dusan Petranovic, EDPS, Electronic Design Process Symposium, Frank Schirrmeister, Gary Smith, Grant Martin, Hans Spanjaart, Herb Reiter, Ian Ferguson, James Colgan, Jim Hogan, Kiron Pai, Marc Greenberg, Mentor, Mike Hutton, Monterey Peninsula, Naresh Sehgal, Phil Marcoux, Qi Wang, Riko Radojcic, Samta Bansal, Sandeep Goel, Sangeeta Aggrwal, Sri Ganta, Steve Leibson, Steve Smith, Steven Pateras, Synopsys, Tom Spyrou
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Thursday, March 15th, 2012
If you missed this week’s Blue Pearl Software workshop in Silicon Valley, you’re in luck – they’re holding it again on April 19th.
These workshops offer not only the opportunity to learn about Blue Pearl’s technologies, they’ll also let you brush up on your acronyms – FPGA, ASIC, SOC, CDC, SDC, SV, VHDL, and RTL – though not necessarily in that order.
Blue Pearl sells a suite of tools offering “comprehensive RTL analysis, clock-domain crossing [CDC] checks, and automated Synopsys Design Constraints [SDC] generation for FPGA, ASIC, and SOC designs.”
Release 6.0 was announced in February at DVCon 2012, where I spoke with Shakeel Jeeawoody, Director of Product Marketing at Blue Pearl.
Jeeawoody said, “We provide tools for linting, clock-domain crossing, and automated SDC generation – things people use to constrain their synthesis. Here in Release 6.0, a major new feature includes language coverage. (more…)
Tags: Altera, ASIC, Blue Pearl Software, CDC, clock-domain crossing, FPGA, RTL, RTL analysis, SDC, Shakeel Jeeawoody, SOC, Synopsys, Synopsys Design Constraints, SystemVerilog, Verific, Verilog, VHDL
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