What's PR got to do with it? Posts Tagged ‘Atrenta’Atrenta acquires NextOp – Could this be the start of something BIG?Wednesday, June 20th, 2012
Gary Smith’s statement about the Atrenta acquisition of NextOp has been bandied about this morning in the news….“This could be the start of something big, and NextOp was an excellent place to start.” See today’s news and analysis about Atrenta’s acquisition of assertion synthesis vendor NextOp plus an interview with Atrenta and NextOp execs in the following online publications: EDA Café Blog: What Would Joe Do?
————– Lee PR does work for Atrenta Atrenta buys NextOpWednesday, June 20th, 2012
Atrenta Accelerates Growth in Front End Design with Acquisition of NextOp Software, Inc. SpyGlass design productivity enhancements expanded to functional verification for semiconductor and consumer electronics developers SAN JOSE, Calif — June 20, 2012 — Atrenta Inc., a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries, today announced that it has acquired NextOp Software, Inc., a leading provider of assertion synthesis technology. Atrenta’s products focus on improving efficiency and reducing cost for the design of complex semiconductor IP and system-on-chip (SoC) devices while NextOp’s products focus on improving efficiency and reducing cost for the functional verification of IPs and SoCs. The combination of both company’s products creates a more complete SoC Realization platform. The acquisition of NextOp allows Atrenta to expand its de-facto standard SpyGlass® register transfer level (RTL) platform to include functional verification — an important and costly component of advanced SoC design. Utilizing patented static and formal analysis techniques, the SpyGlass platform currently provides RTL design efficiency improvements in the areas of linting, clock synchronization, power optimization, testability, timing constraints and physical routing congestion. The SpyGlass platform will now be expanded to include functional verification support using NextOp’s patented dynamic assertion synthesis technology, resulting in verification efficiency improvements for semiconductor and consumer electronics developers. “The addition of NextOp’s functional verification technology will give our customers a distinct advantage by providing complete coverage of front end design activities,” said Dr. Ajoy Bose, chairman, president and CEO of Atrenta. “Atrenta’s customers have come to rely on SpyGlass to verify a broad range of design intent, but functional verification was a missing part of our platform. NextOp’s assertion synthesis completes this part of our offering – Atrenta customers will now have added confidence that their designs will work as expected while meeting schedule and performance requirements. We are very excited to bring these innovative solutions and the resulting expanded benefits to our large customer base. ” “Atrenta is one of the largest private EDA companies,” said Dr. Yunshan Zhu, president and CEO of NextOp Software. “NextOp has pioneered assertion synthesis technology. Our tool is now widely deployed in production at multiple tier 1 customers – many of whom also use SpyGlass. Atrenta’s world-class field operation will further accelerate the mainstream adoption of assertion synthesis.” “I’ve heard good things about NextOp’s verification technology from some impressive customers – the combination of Atrenta’s RTL design and NextOp’s RTL verification technology will improve the entire SoC Realization process,” said Jim Hogan, EDA industry veteran and private investor. “I’m also glad to see private/private acquisitions like this happening again after such a long dry spell. Atrenta could be leading a trend in renewed growth for the EDA sector.” “With the acquisition of Magma there has been renewed talk about a roll-up in the middle of the EDA community,” saidGary Smith, founder and chief analyst for Gary SmithEDA. “The most obvious candidates are the RTL sign-off tool vendors, and the most talked about driver, of the roll-up, has been Atrenta. This could be the start of something big, and NextOp was an excellent place to start.” NextOp’s BugScope assertion synthesis tool will be sold and supported by the combined Atrenta/NextOp worldwide field organization. Dr. Yunshan Zhu will assume the role of vice president, new technologies reporting to Dr. Ajoy Bose. Dr. Yuan Lu, co-founder and CTO of NextOp will assume the role of chief verification architect reporting to Dr. Zhu. Financial terms of the transaction were not disclosed. About Assertion Synthesis Assertion synthesis leverages design and test bench information to automatically generate high quality assertions and functional coverage properties. Generating assertions and coverage properties manually is tedious and error-prone. Assertions represent a machine-readable version of design intent and are used to improve verification completeness. Functional coverage properties identify functional coverage deficiencies providing guidance for verification teams. When used together, design teams can reduce functional verification time and improve overall functional coverage, resulting in lower design costs, better first-time silicon success and improved quality. About Atrenta Atrenta’s SpyGlass® Predictive Analysis software platform significantly improves design efficiency for the world’s leading semiconductor and consumer electronics companies. Patented solutions provide early design insight into the demanding performance, power and area requirements of the complex system on chips (SoCs) fueling today’s consumer electronics revolution. More than two hundred companies and thousands of design engineers worldwide rely on SpyGlass to reduce risk and cost before traditional EDA tools are deployed. SpyGlass functions like an interactive guidance system for design engineers and managers, finding the fastest and least expensive path to implementation for complex SoCs. SpyGlass from Atrenta: Insight. Efficiency. Confidence. www.atrenta.com About NextOp Software NextOp Software, Inc. is focused on delivering assertion-based verification solutions that allow design and verification teams to uncover bugs, expose functional coverage holes, and increase verification observability. NextOp’s BugScope assertion synthesis is the first product to automatically generate whitebox assertions and functional coverage properties in SVA, PSL and Verilog formats. BugScope’s properties are used to drive progressive, targeted verification via robust, executable design specifications for existing simulation, formal and emulation flows. The company is headquartered at2900 Gordon Avenue, Suite 100,Santa Clara,CA95051. For more information, visit www.nextopsoftware.com or call +1 408-830-9885. ******************************************************* © 2012 Atrenta Inc. All rights reserved. Atrenta, the Atrenta logo and SpyGlass are registered trademarks of Atrenta Inc. BugScope and NextOp are trademarks of NextOp Software, Inc. All others are the property of their respective holders. This press release contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this press release.
—————————- Lee PR does work for Atrenta
The SpyGlass® value interviewsFriday, June 1st, 2012
Atrenta has pulled together quite a slate of customers, partners, an industry observer and EDA’s premier investor to talk about the value SpyGlass brings to each of their realms. It’ll be interesting to hear how this signature product has proliferated in different environments! Atrenta invites you to stop by and hear how SpyGlass improves productivity @ Xilinx, Vivante, Sonics and Arteris and why Dan Nenni and Jim Hogan see SpyGlass as the consummate ubiquitous product in EDA. The talks will be held at Atrenta’s booth #2230. Monday, June 4 9:30 am…..Jack Browne, Sonics Tuesday, June 5 10:30 am…Charlie Janac, Arteris Wednesday, June 6 10:30 am…Charlie Janac, Arteris ………………………. Powering up at DAC with Atrenta’s Kiran VittalThursday, May 31st, 2012
Ed: So power, or rather more rigorous power management will be a hot topic at DAC. How come? What will be different this year? Kiran: As we all know, power is of the biggest concern to both mobile applications as well as wired devices. An average mobile SoC is over 100M gates operating at over 500Mhz and designers do everything necessary to apply all known power management techniques to reduce power. It will also be interesting to see that application processors for cloud-based servers are now being designed with over 10 power domains to shut off power in non operating regions and a quad core SoC consumes around 5 watts during maximum utilization and as little as 0.5 watts during idle time. Ed: So what approaches are we going to hear about @ DAC? Kiran: We are going to hear about power management, power intent creation using standards, power optimization, power verification and sign off. Ed: How do they stack up? Kiran: It is very clear that any power management and optimization technique applied at the gate level is too late to make any difference to the aggressive low power requirements. Early power planning, RTL power estimation, automated reduction around both registers and memories and early power intent verification is the only way to achieve today’s aggressive power goals for both mobile as well as wired chips. Stop by Atrenta’s booth (#2230) to talk about Kiran’s views with him!
Note: Lee PR does work for Atrenta Atrenta’s unified platformTuesday, May 15th, 2012
Maybe Atrenta is saying goodbye to the thought-bubble guy….. Atrenta’s SpyGlass has always been the dominant name in the company’s brand portfolio,and for good reason. It’s the dominant product in RTL design analysis, verification and optimization. Now, Atrenta is reconfiguring its product lineup to formalize this state of affairs. SpyGlass now becomes the unifying platform for all Atrenta products. Sort of the mother ship that all Atrenta products are based on. So what’s a unified platform? All the tools now share a common set up and debugging methodology and tighter GUI. And what can users verify and optimize from this new unified platform? Syntax, power, testability, clock synchronization, timing and routing congestion. All at the RTL stage, well before detailed implementation begins. Predictions 2012 – Persistence of MemoryThursday, February 9th, 2012To finish off our series of predictions, I would like to point you to another series of interesting and informative prophesies. Click on the following topics to see these predictions collected by Brian Bailey, Editor of EDA DesignLine.
A big THANK YOU from Ed & me (Liz) to all who shared their eye opening predictions with us. Click on their names to see their predictions. Mike Gianfagna, Karen Bartleson, Paul McLellan, Jens Andersen, Bob Smith, Steve Schulz, Mathias Silvant, Herb Reiter, Max Maxfield, Chris Edwards, John Barr.
Only time will tell……
 The Persistence of Memory, 1931, Salvador Dali
Predictions 2012 – ConsolidationMonday, January 16th, 2012
I think that there will continue to be consolidation in the EDA industry. At each process node, fewer and fewer designs ship in high enough volume to recover the enormous investment in bringing them to market, which is a bad trend for EDA. Several companies in the ecosystem will go public if the market conditions remain favorable: eSilicon, Tensilica, Atrenta. Although, as with Apache, they may get acquired at the last minute (at high valuations). Mentor may get acquired, or sell off some business lines. Paul McLellan
Predictions 2012 – Mergers and 3DWednesday, January 11th, 2012And the predictions begin……
With regard to “Events” – 2012 will be a year of further acquisition and consolidation for both the EDA and IP industries. Some new faces will join the dance, with significant resources at their disposal. It is likely the “Big 3” will have at least one new name in a year’s time. With regard to “Breakthroughs” – it’s a different story. 3D stacked-die design still won’t be mainstream in a year’s time. True hardware/software co-design will still be a developmental area and verification will still be as hard as ever. Many panels, blogs, seminars and special conference sessions will debate these topics throughout the year with great hope and excitement, however. Mike Gianfagna
Finding Love at DAC…..at AtrentaSunday, June 19th, 2011You saw the trailer……
Are you curious what happened next….whether this young man found love…..at DAC? In case, you missed it – here’s the rest of the story……
BTW the CTO of the SoC Realization Company expresses his views on the future of the technology and business of EDA and what’s needed in EDA tools in this video on System-Level Design…..
Full Disclosure: Lee PR works for Atrenta.
Follow us on Facebook DAC frenzy is hitting!Wednesday, May 11th, 2011We’re 25 days and counting to the annual industry conference, DAC. As always, people are talking…what’s the theme this year? This young man has an idea…..
Click here to find out what it is Last year, EDA360 was the at- & post-DAC talk of the town, so to speak. So is there any continuity this year? Atrenta seems to have made the first move in making the EDA360 vision real. It’ll come out of the chute as “The SoC Realization Company,” and probably show technology that implements SoC Realization. By doing that, Atrenta may end up helping define the industry direction on how the EDA360 rubber meets the road. Here is a white paper that talks about HOW to realize SoC Realization: Click here to read the white paper …………………………………. Stay tuned………next week, details on how to find out what Jim Hogan and Paul McLellan have to say about the direction EDA ought to follow so EDA & IP companies can answer their investors who demand that they “Show me the Money!”
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