What's PR got to do with it? 
Ed Lee
Ed Lee has been around EDA since before it was called EDA. He cut his teeth doing Public Relations with Valid, Cadence, Mentor, ECAD, VLSI, AMI and a host of others. And he has introduced more than three dozen EDA startups, ranging from the first commercial IP company to the latest statistical … More » What is in-situ de-embedding?January 14th, 2016 by Ed Lee
As a follow up to Chris Scholz’s predictions on 2016 signal integrity trends, we checked in with in-situ de-embedding inventor Dr. Ching-Chao Huang, who gives us a more detailed look at how engineers will need to handle signal integrity measurement and calibration for high-speed boards.
Ching-Chao: We first coined the term “In-Situ De-embedding” (or ISD) for the de-embedding software we launched in 2011. It was a new approach to remove the non-causality artifact commonly found in other de-embedding methods. Ed: What was the problem you saw coming? Ching-Chao: Accurate de-embedding is crucial to characterize the electrical performance of a component, from chip to package, PCB, connector and cable. A Vector Network Analyzer (VNA) is perhaps the best equipment to use for characterization because it measures the detailed electrical behavior of a component at every frequency. However, a component, or device under test (DUT), does not usually lend itself to direct measurement and needs to be mounted on a fixture for connection to the VNA. The effect of the fixture needs to be removed (i.e., de-embedded) in order to get the true electrical behavior of the DUT itself. Ed: So how did the electrical behavior get measured before? Ching-Chao: The traditional approach is to fabricate and measure test coupons that resemble the fixture’s lead-ins and/or lead-outs. Information is extracted from the test coupons and de-embedded from the fixture + DUT measurement data. To collect more information, the TRL (thru-reflect-line) calibration method requires that multiple test coupons be built. This method takes up a fair amount of board space. Thru-reflect line vs. in-situ de-embeddingJanuary 11th, 2016 by Ed Lee
 Chris Scholz Today we wrap up our interview with Chris Scholz, Product Manager, Vector Network Analyzers, R&S North America, discussing the different approaches to Signal Integrity. Ed: It’d be great if you could give us a brief comparison on approaches you’ve dealt with. Chris: Sure! Signal Integrity applications use baseband data with bandwidth up to 10s of GHz impedance, matching of DUTs in Signal Integrity applications is relatively poor. Looking at TRL-based calibration techniques that have been automated by some vendors, these techniques generally fail to provide accurate results beyond a few GHz. Ed: What’s TRL? Chris: Thru-reflect line. For our customers, in-situ de-embedding (ISD) has shown to be the most accurate de-embedding technique available to date. One of the nice side effects of ISD is that it results in causal measurements what are beneficial for further processing standard design tools. Because the Signal Integrity engineers deal with baseband signals, they face a set of unique challenges that are marginally important for RF engineers. For wireless systems, transmission channels are narrow band and separated from each other. By contrast, Signal Integrity deals with baseband signals. This means that signals experience impairments that span from close to DC to the maximum frequency that the channel supports. This also means that digital signals are prone to picking up low frequency impairments such as power supply noise, they are prone to frequency dependent loss at high frequencies and they pick up broadband impairments such as various types of crosstalk. What tools will SI Engineers need in 2016?January 7th, 2016 by Ed Lee
Chris Scholz Today’s excerpt with Chris Scholz, Product Manager, Vector Network Analyzers, R&S North America, focuses on the SI tools that engineers will need to meet the SI challenge in 2016. Ed: What tools do you see engineers using and how well do they handle this oncoming SI challenge? Chris: Vector Network Analyzers have the reputation of being complicated and were considered a specialist tool for ultra-precise measurements and for calibration labs. This SI tool technology has changed, for the better. Today’s modern computing technology and graphic user interfaces arm any lab technician (with minimal training) to produce reliable and trustworthy VNA measurements. So with modern VNAs, you get the best of both worlds: precise measurements to a well-defined reference plane and ease of use of a modern test tool. This is of special interest for SI applications where test strategies are traditionally centered around time-domain measurements such as eye diagrams, jitter margins, equalizers and time-domain reflectometry. Today’s VNAs can perform all these measurements and the results tend to be more accurate and repeatable than with traditional tools. High speed designs require new ways to handle Signal IntegrityJanuary 4th, 2016 by Ed Lee
Chris Scholz We recently had a chance to sit down with Chris Scholz, Product Manager, Vector Network Analyzers, R&S North America at German electronic equipment manufacturer Rohde & Schwarz. For those of us who aren’t familiar with Rohde & Schwarz, it’s a worldwide electronics group company with business fields in test and measurement, broadcast and media, secure communications, cybersecurity and radio monitoring/radio location. Based in Munich, R&S was founded in 1933 and has had a U.S. presence for years. We got together with Chris to hear what was the big design issue his engineers were encountering as 2016 approached. Here’s what he had to say. Today’s excerpt gives us some background on Rohde & Schwarz and Signal Integrity. Ed: Chris, before we get into the heart of our discussion, it might be good to give us a brief rundown on who Rohde & Schwarz is. Chris: Sure, Ed. Rohde & Schwarz is primarily known for our leadership in RF, microwave and millimeterwave technology. We were founded in 1933 and are based in Munich. We have close to 10,000 employees. Design rules built on quicksand?May 27th, 2015 by Ed Lee
Sage CEO Coby Zelnik recently talked with us about how design rules need a formal methodology to account for all the permutations of each rule for today’s and the next generation’s chip designs. What I found alarming was that he noted how design rules are being built today. An engineer writes the rule based on…well, based on…um…gut feel? The point is that the design rule creation process currently has no specification to govern the creation of the design rule. Silicon RisingMay 3rd, 2015 by Ed Lee
I felt like I was part of the US steel industry and living in the rust belt. 😉 So it was quite a pleasant surprise to get the invitation to Silicon Sunrise, a coming out event put on by a new, months-old organization, Silicon Catalyst. And I was curious, as I bet the other invitees and attendees were. It looked like Silicon Catalyst was a new investment organization that possibly focused on silicon. S parameters have to be accurate…does in-situ de-embedding work?March 10th, 2015 by Ed Lee
One that’s garnering some thinking and observer attention is signal integrity for high(er) speed board designs. With most all designs running at 10 Gbps (more mainstream these days), and approaching 25 Gbps, current measurement and verification of S-parameters seems to be an increasing concern. At DesignCon, SI authority Erig Bogatin and Industry observer Max Maxfield discussed different aspects of this problem with AtaiTec CEO Ching-Chao Huang. Read the rest of S parameters have to be accurate…does in-situ de-embedding work? What was he thinking?October 27th, 2014 by Ed Lee
Jim Hogan and Bernard Murphy on IoT Security: How the human body’s defense mechanism may be the model for repelling attacks on the IoTOctober 16th, 2014 by Ed Lee
This article by Atrenta’s CTO Bernard Murphy and investor Jim Hogan has attracted a lot of interest. Murphy and Hogan say that we can draw inspiration from biology on how to design the IoT fortress: specifically, how the human body wards off attacks from bacteria, viruses, other bad and harmful stuff. And they describe in detail the concept on how electronic engineers can plan to do so. It’s an intriguing piece that gives electronic designers a first huge step on how to secure the IoT and keep those of us who are IoT-interconnected – Borg Collective like – protected from the inevitable cyber attacks. Biology, Deceit & Security in the Internet of Things What do you think? AtaiTec co-author shows how reducing skew can improve a channel’s insertion-loss-to-crosstalk-ratioOctober 8th, 2014 by Ed Lee
AtaiTec Corp. president Dr. Ching-Chao Huang co-authored a DesignCon 2014 paper that looks at new methodologies to characterize connectors for 25+ Gbps boards. What’s eye opening is how the authors used AtaiTec’s In-Situ De-embedding (ISD) software to extract connector-only data from a large board and compare them directly with simulation results from a 3D field solver. Learn more about this finding here: http://ataitec.com/docs/5-TH2Paper_NewMethodologyFor25+Gbps.pdf
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