Posts Tagged ‘Atrenta’
Thursday, October 16th, 2014
This article by Atrenta’s CTO Bernard Murphy and investor Jim Hogan has attracted a lot of interest.
Murphy and Hogan say that we can draw inspiration from biology on how to design the IoT fortress: specifically, how the human body wards off attacks from bacteria, viruses, other bad and harmful stuff.
And they describe in detail the concept on how electronic engineers can plan to do so.
It’s an intriguing piece that gives electronic designers a first huge step on how to secure the IoT and keep those of us who are IoT-interconnected – Borg Collective like – protected from the inevitable cyber attacks.
Biology, Deceit & Security in the Internet of Things
What do you think?
Tags: Atrenta, Bernard Murphy, Biology, Borg Collective, Chip Design, cyber attack, Cyber Security, EDA, EDA & IP, Electronic Design Automation, https://www.facebook.com/pages/Lee-Public-Relations/201964499825219?ref=hl, Internet of Things, IoT, Jim Hogan, Lee PR, Lee Public Relations, Security, Semiconductor IP, semiconductors, SoC, Star Trek: Next Generation, System on Chip, VistaVentures LLC, www.leepr.com
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Thursday, July 24th, 2014
Bernard Murphy, CTO of Atrenta, talks about the challenges to security that the IoT will bring in our continuing coverage of the IoT panel at DAC…and sees the IoT as a lot like a biological system!!!!
 Murphy: The IoT represents a new level of challenge for security – not just because you have to worry about automotive, medical and so on. But also, if you believe the numbers, then the number of potential edge nodes in an IoT is on the order of a trillion or more. That’s two to three orders of magnitude bigger than any existing network you can imagine. It’s about the number of cells you find in a new born baby.
So a trillion edge nodes looks like a biological system. Why is that relevant? Because our approach to security today is very atomic….It’s not a system level approach. You think in terms of system level and you look at analogies with biological systems, then you think in terms of different things.
Of course, you need all the antibodies and antiviruses. But you also want to think about things like signaling – help I’m under attack. It’s not the same thing as defending yourself. You still want to defend. But you also want to signal to your nearest neighbors or an organization around you that you’re under attack. It can isolate you or send in defenses.
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Tags: 51DAC, Atrenta, Chip Design, DAC, Design Automation Conference, EDA, Electronic Design Automation, https://www.facebook.com/pages/Lee-Public-Relations/201964499825219?ref=hl, Internet of Things, IoT, Jim Hogan, Lee PR, Lee Public Relations, Security, semiconductors, SoC, System on Chip, www.leepr.com
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Monday, July 21st, 2014
As we had previously announced, venture capitalist Jim Hogan moderated a panel at DAC regarding the IoT.
It was an eye opener about all things IoT……or maybe we should call it the IoE (The Internet of Everything), or as one prominent editor noted, the IoW (The Internet of Whatever). Our panelists included: Gary Smith, Market Analyst, GSEDA; Frank Schirrmeister, Group Director, System Development Suite, Cadence; Bernard Murphy, CTO, Atrenta; and Randy Smith, VP of Marketing, Sonics.
Very lively discussion among panelists, but also from the floor! Most notably editor Gabe Moretti of Chip Design and Simon Bloch of Samsung. Bloch, Sr. Director of R&D in mobile consumer wireless devices, posed questions and stimulated discussion to the point where he might be called the unannounced 6th panelist.
Over the next few blogposts, we’ll share snippets of that discussion. Gary Smith will start us off…..
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Tags: 51DAC, Atrenta, Bernard Murphy, Cadence, Chip Design, DAC, Design Automation Conference, EDA, EDA & IP, Electronic Design Automation, Frank Schirrmeister, Gary Smith, GSEDA, https://www.facebook.com/pages/Lee-Public-Relations/201964499825219?ref=hl, Internet of Things, IoT, IP, Jim Hogan, Lee PR, Lee Public Relations, Randy Smith, semiconductors, SoC, Sonics, System on Chip, VC, Wall Street, www.leepr.com
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Tuesday, May 20th, 2014
As DAC frenzy hits us all, here’s an event that EDA/IP users and media people ought to consider attending.
It’s a Jim Hogan-moderated discussion event on
IoT system design concerns
Jim will 1) introduce the topic; 2) spur, moderate, provoke discussion and 3) sum up what we’ve learned during this session. Of course, this group of speakers are pretty opinionated and won’t need much provocation.
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Tags: Atrenta, Bernard Murphy, Cadence, Chip Design, DAC, Design Automation Conference, EDA, EDA & IP, Electronic Design Automation, Frank Schirrmeister, functional verification, Gary Smith, GSEDA, https://www.facebook.com/pages/Lee-Public-Relations/201964499825219?ref=hl, Internet of Things, IoT, Jim Hogan, Lee PR, Lee Public Relations, Randy Smith, register transfer level, RTL, semiconductors, SoC, Sonics, System on Chip
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Monday, March 17th, 2014
 RTL Signoff is certainly one of the hot topics in chip design circles lately, and one that is garnering great interest and concern. I chatted recently with Piyush Sancheti, VP of Marketing at Atrenta, on what it is, why it’s a design imperative, and how it should be done.
Liz: Piyush, thanks for taking the time out to chat with me today on this vital topic…RTL Signoff.
Piyush: No problem, Liz
Liz: So, to start out, what is RTL Signoff?
Piyush: “RTL Signoff” gained momentum as an established concept in 2013. While the concept is not new, a commonly-accepted definition did not exist in the past, which is now beginning to emerge. Here’s what I think RTL Signoff is: a comprehensive series of well-defined MUST-pass requirements for your RTL before you commit the design to downstream implementation such as synthesis and physical layout. In addition to this complete set of RTL Signoff requirements, you need tools and methodologies to meet the requirement, along with tangible metrics to measure your pass/fail criteria.
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Tags: Atrenta, Chip Design, EDA, EDA & IP, Electronic Design Automation, https://www.facebook.com/pages/Lee-Public-Relations/201964499825219?ref=hl, Intellectual property, IP, Piyush Sancheti, register transfer level, RTL, RTL signoff, Semiconductor IP, semiconductors, SoC, System on Chip, www.leepr.com
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Monday, February 3rd, 2014
 Robert Beanland, Senior Director, Corporate Marketing at Atrenta, weighed in on what EDA and IP vendors need to do in 2014.
“Ahhh, the age old question of, ‘What does EDA and IP need to do this year?’ Well, …
The IP folks need a way to provide fully validated IP to their customers with not only a good understanding of all the validation that has been done, but also the expected use model and configurations for the IP. The use model is critical because it is quite common for IP to be ‘abused’ in a way or mode that the IP vendor never expected. When this happens, the customer must be able to assess the problem in-situ and work with the IP vendor to find a resolution. A standardized quality metric is much more desirable than the current option of comparing each vendor’s unique assessment of their validation. This validation and analysis should include, but is not limited to, power, clock domains, testability and physical. The ‘clean’ IP can then be used with more confidence by their customers in their SoC integration.
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Tags: Atrenta, Chip Design, EDA, EDA & IP, Electronic Design Automation, https://www.facebook.com/pages/Lee-Public-Relations/201964499825219?ref=hl, Intellectual property, IP, Lee PR, Lee Public Relations, RTL, Semiconductor IP, SoC, System on Chip, www.leepr.com
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Monday, January 27th, 2014
 We asked Mike Gianfagna, VP of Marketing at eSilicon and former VP of Corporate Marketing at Atrenta, about EDA, IP and the chip industry in 2014.
Ed: What does EDA and IP need to do in 2014?
Mike: Work more effectively with each other. IP integration continues to be a huge bottleneck for SoC design. A more uniform quality metric and a way to enforce it is desperately needed. This problem can’t be solved in isolation. EDA and IP companies need to collaborate to tame this issue. They can do it.
Ed: What does the chip industry want from EDA and IP in 2014?
Mike: The same thing really. Every SoC project is dependent on somebody’s IP. Whether it’s internally supplied or provided by your favorite IP supplier or your favorite ASIC supplier, the requirement for easy integration with no surprises is the same. Better collaboration between members of the SoC supply chain will definitely help.
Tags: 2014, Atrenta, Chip Design, EDA, EDA & IP, Electronic Design Automation, https://www.facebook.com/pages/Lee-Public-Relations/201964499825219?ref=hl, Intellectual property, IP, IP integration, Lee PR, Lee Public Relations, Semiconductor IP, semiconductors, SoC, System on Chip
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Monday, September 30th, 2013
There’s an EDA industry reunion at the Computer History Museum on October 16th. “EDA: Back to the Future” is being put on by EDAC along with several sponsors, and it looks like it will be a night to remember. To learn more about the event and purchase tickets click here.
Part of this event is a fund raising auction. I recently talked with Mike Gianfagna at Atrenta about the auction to understand what that part is all about.
Ed: Mike, I understand that part of the event on October 16th is a fund raising auction. Can you tell me a little about that?
Mike: Sure Ed. The Computer History Museum is working on an exhibit for EDA – one that captures the rich history of this industry and preserves some of its innovation in the form of physical artifacts and some of its pioneers in the form of oral histories, captured on video. It’s a terrific project, but we need money to keep the progress going. The auction on the evening of October 16th is focused on raising that money.
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Tags: Atrenta, Computer History Museum, EDA, EDA Consortium, EDAC, Electronic Design Automation, https://www.facebook.com/pages/Lee-Public-Relations/201964499825219?ref=hl, semiconductors, SoC, System on Chip
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Wednesday, August 28th, 2013
Atrenta will discuss what RTL signoff requirements are needed for SoC designers in China, South Korea and Taiwan at their upcoming seminars in September and October.
Click here for more information.
LPR does work for Atrenta
Tags: Atrenta, Chip Design, EDA, EDA & IP, Electronic Design Automation, https://www.facebook.com/pages/Lee-Public-Relations/201964499825219?ref=hl, Intellectual property, IP, Lee Public Relations, register transfer level, RTL, RTL signoff, Semiconductor IP, semiconductors, SoC, System on Chip
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Tuesday, August 20th, 2013
We often think that we’ve got the timing job nailed down and that there aren’t any problems that we can’t easily, almost routinely solve. Using timing exceptions to optimize synthesis or P&R shouldn’t be a problem.
However, making an error when specifying timing exceptions can possibly shut down a design project.
Take a look at what Atrenta’s Shaker Sarwary, Ramesh Dewangan and Sridhar Gangadharan say about how to avoid this situation:
http://alturl.com/99bbs
(Note: white paper download requires registration)
LeePR does work for Atrenta.
Tags: Atrenta, EDA, Electronic Design Automation, https://www.facebook.com/pages/Lee-Public-Relations/201964499825219?ref=hl, Lee Public Relations, register transfer level, RTL, semiconductors, SoC, SpyGlass, System on Chip, Timing Constraints
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