Search Results
Thursday, August 22nd, 2013
Tags: Aldec, ansi-c, c/systemc code, dac, design, distributorship, hls, ide, nec cyberworkbench, qor visualization tool, rtl simulation, SoC, SoC and ASIC Prototyping, systemc, Validation, verification, verification process
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Monday, August 12th, 2013
Tags: Aldec, design, design subset of systemverilog, fast track online trainings, simulation, system verilog, training, verification, verilog, VHDL
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Tuesday, July 30th, 2013
Tags: active-cad, active-cad format, Active-HDL, Aldec, design, eda tools, edif netlist, importing legacy schematic based designs, schematic tools, verilog, VHDL, viewdraw, viewlogic, Xilinx, xilinx foundation series, xilinx virtex
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Wednesday, July 24th, 2013
Tags: acceleration, Aldec, asic gates, FPGA, fpga boards, fpga-based prototyping boards, hardware acceleration, Hardware Emulation, HDL, hdl simulation, hes design verification manager, HES-DVM, Riviera-PRO, rtl simulator, soc design, system-on-chip verification cycle
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Monday, July 22nd, 2013
Tags: accelerate dsp design development, Aldec, co-simulation, data analysis, data visualization, debugging, design, dsp algorithm, eda industry, edif cells, hdl code, hdl simulator, matlab, Riviera-PRO, simulink, verification, verilog modules, vhdl entities
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Wednesday, June 26th, 2013
Tags: Aldec, compliance, do-254, FPGA, fpga interface, pld vendors, safety-critical, SoC, standards, verification
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Monday, June 24th, 2013
Tags: Active-HDL, auto-formatting, c/c++, code analysis, code browser, code folding, code navigation, code template, columns selection, creating hdl text modules, HDL, hdl editors, on-the-fly error detector, ova, perl scripts, psl, syntax highlighting, system verilog, systemc, Tcl scripts, templates, value probes, verilog, VHDL
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Monday, June 17th, 2013
Tags: device development life cycle, downstream traceability, FPGA, HDL Design, hdl functions, Impact Analysis, post-layout design, spec-tracer, suspect links, test results, Testbench, Traceability, upstream traceability, verification test cases
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Tuesday, June 11th, 2013
Tags: cdc, dac, design automation conference, driver software verification, ecosystem partners, fpga-based prototyping, Functional Verification, high level synthesis, hls, hw/sw co-verification, mixed-signal simulation, multimillion gate soc, multiple clock domains, Riviera-PRO, SoC, SoC and ASIC Prototyping, SoC Verification, spec-tracer, system development, system verilog, systemverilog-based uvm, uvm-compliant environments, verification, verification ips, vips
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