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Posts Tagged ‘HES-DVM’

Partition your Design for FPGA Prototyping

Monday, December 11th, 2017

Modern ASIC and SoC designs have increased in complexity such that multiple FPGAs of the largest capacity are now required to prototype the entire functionality of the design. As design sizes increase, more and more FPGAs are required. The capacity and pin limitations of FPGAs create constraints for how the ASIC/SoC design can be mapped into the FPGAs. Aldec’s HES-DVM’s prototyping mode accounts for the limitations of the target FPGAs and allows the user to map a design to the FPGAs within these constraints.

Partitioning a design to fit into multiple FPGAs can be a lot of work

Designing the partitions with HES-DVM is as easy as selecting specific VHDL/SystemVerilog design modules from the hierarchy and moving them to a desired partition. All information about the design modules and the amount of LUTs, Flip-flops, memory blocks, DSP slices, and I/O consumed are displayed for convenience. These values can also be viewed as a percentage of the target FPGAs’ available resources allowing you to know when an FPGA is full.

Adding a module to a partition

Mapping a partition to an FPGA

Once the partitions are finalized, each partition can be assigned to a specific FPGA. A design successfully fitting into the FPGAs on the target prototyping board is only the beginning. There still remains a big problem with the sheer number of connections between the partitions. Modern designs have thousands of internal signals interconnecting major blocks or sub-systems. It’s likely that there won’t be a sufficient amount of direct connections between FPGAs to support the design’s internal wiring. How can the large amount of internal design signals possibly be accommodated by the relatively smaller amount of I/O available from the FPGAs?

For the rest of this article, visit the Aldec Design and Verification Blog.

Emulation on the Cloud: HES Cloud delivers access to a high performance emulation platform

Thursday, June 15th, 2017

‘The cloud’ has been an industry buzz word for some time now and whilst the initial focus was on data storage and sharing – and spawned the likes of Dropbox – ‘cloud computing’ is currently the latest trend. For instance, Amazon’s cloud platform, Amazon Web Services (AWS), gives users access to servers and a range of applications. Storage is available as before but so too now are dedicated relational databases; which in Amazon’s case is provides through a different service.

Enterprise businesses are taking advantage of cloud computing platforms, and for a number reasons. These include pay-as-go (as opposed to investing considerable cap ex), speed and flexibility (resources and storage can be made available quickly), and one is spared the headache of maintaining a mass of IT hardware and keeping on top of software license renewals.

Also, earlier this year Amazon announced EC2 (Elastic Compute Cloud) F1, a compute instance with FPGAs that users can program to perform hardware accelerations. The F1 instance includes an FPGA developer Amazon Machine Image (AMI) which includes a development environment with scripts and tools for code compilation and design simulation.

It is expected the primary users of EC2 F1 will be software developers, working on complex and compute-intensive algorithms for which FPGAs lend themselves particularly well. For instance, High Performance Computing will increasingly exploit FPGA technology.

But let’s not forget one of the most important roles that FPGAs have been playing in our industry – EDA – for a number of decades: hardware acceleration for ASIC prototyping purposes.

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How Can Verification IPs Help the SoC Testing Process?

Monday, April 20th, 2015

 

How to use VIPs In Practice

figure 0
Let’s assume that we are designing a new system on chip (SoC) which contains a processor and memory controller, as well as analog and digital peripherals like Ethernet, USB, 1-Wire and JTAG controllers.

Allow me to describe a typical verification process, and explain why I recommend the use of Verification IPs within the testing process.

Figure1 typical verification process
Figure 1. Typical verification process

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Scaling the “Internet of Things”

Wednesday, January 21st, 2015

Internet-of-thingsHappy New Year!

January brought an unseasonably warm wave of weather to Las Vegas as International CES converged on the city this month.

The size and scope of this worldwide consumer electronics tradeshow continues to grow each year with new products and industries on the rise, now driven by a phenomenon called the “Internet of Things” (IoT).

Shawn Dubravac, Ph.D., Chief Economist and Director of Research for the Consumer Electronics Association (CEA) kicked off the event by presenting a summary of his new book, “Digital Destiny”.

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How HES™ Technology Solved Problems for These Users

Monday, October 20th, 2014

HES_USE_CASESRecognizing a problem that engineers are facing and developing a solution has been Aldec’s rather straight-forward mantra for going on thirty years now. Aldec launched its Hardware Emulation Solutions (HES) product in 2003, integrating RTL simulation with hardware emulation, and offering hardware and software design teams the ability to work concurrently. Today HES™ is a fully automated and scriptable HybridVerification and Validation environment for SoC and ASIC designs capable of bit-level simulation acceleration, SCE-MI 2.1 transaction emulation, hardware prototyping, and virtual modeling.

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Biggest Hits and Trends from ARM TechCon

Wednesday, November 6th, 2013

The recent ARM® TechCon Conference in Santa Clara was definitely the front-runner of my favorite conferences that I attended this year. Fun, informative and filled with software engineers, physical designers, design verification teams, and hardware engineers – ARM TechCon was the place to be to learn about the latest innovations from the embedded industry. Aldec was there showcasing our HES-DVM™ and HES-7™ platforms, which enable engineers to utilize emulation and FPGA-based prototyping to verify the latest ARM designs.

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Integrating SystemVerilog and SCE-MI for Faster Emulation Speed

Wednesday, October 9th, 2013

In the last SCE-MI article, we discussed how SCE-MI macro-based infrastructures can speedup SoC design verification time. In SCE-MI 2.1, Accelera introduced a ‘function-based’ infrastructure which is based on SystemVerilog DPI functionality. The SystemVerilog DPI is an interface which can be used to connect SystemVerilog files with foreign languages (C, C++, SystemC, etc).

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Leverage Hardware Acceleration for Faster Simulation

Wednesday, July 24th, 2013

Breaking the Bottleneck of RTL Simulation

Utilizing hardware acceleration in a System-on-Chip verification cycle can speed-up HDL simulation runs from 10-100x, while providing the robust debugging available from an RTL simulator. Acceleration (also referred to as Co-Simulation) combines the speed of FPGA-based prototyping boards, by offloading resource hungry modules into the FPGA, while non-synthesizable constructs of the testbench remain in the RTL simulator.

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DownStream: Solutions for Post Processing PCB Designs
TrueCircuits: UltraPLL



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