Aldec Design and Verification
Dmitry is a product manager at Aldec responsible for ALINT™ and Riviera-PRO™ product lines. He has over 8 years of digital design and verification experience, including previous roles in corporate and field applications, technical marketing, and software development with R&D divisions of … More »
Back from DAC
June 11th, 2013 by Dmitry Melnik
Functional Verification Insights from Austin
I just returned back to the office from the 50th Design Automation Conference (DAC) which took place in Austin, TX, on June 2—6. As I began compiling my trip report, I thought that I might share some of my observations, especially for those who couldn’t attend this industry event but still wanted to gain some insight.
One of the reasons I like DAC is that it has always been the main industry event, attracting people from all over the world, and provides participants with the opportunity to meet most of their key customers, ecosystem partners, and competitors in a single location. From an exhibitor’s perspective, DAC is mainly about engaging with attendees on the floor, learning about their current and anticipated challenges, and educating them on how they can innovate and succeed using our product offerings.
Presentations and discussions
As usual, Aldec and our ecosystem partners had a productive time at DAC this year, connecting with attendees for a variety of live presentations and demos, showing them the latest advantages in system development, functional verification, mixed-signal simulation, high-level synthesis, and HW/SW co-verification.
We will be hosting a series of upcoming webinars to deliver these sessions to those of you who couldn’t attend. More details can be found here.
Functional Verification trends
Since Aldec’s core competency is functional verification, I was keeping an eye on this particular domain… and just by looking at the exhibiting companies, I can tell that both interest and presence in the functional verification space keep growing from year to year. This is no surprise to any major EDA vendor, as our customers have been designing complex multimillion SoCs for quite a while now.
Well, I could go on and on… as I haven’t even mentioned the challenges associated with low power design, multiple clock domains (CDC), high-level synthesis (HLS), and formal verification. Aldec has been around for 30 years, and we have seen designs evolve from few thousand gates to millions of gates… and today’s multimillion gate SoC will eventually become building blocks (or IPs) for the future SoC designs. These are certainly exciting times for the EDA industry!
Tags: cdc, dac, design automation conference, driver software verification, ecosystem partners, fpga-based prototyping, Functional Verification, high level synthesis, hls, hw/sw co-verification, mixed-signal simulation, multimillion gate soc, multiple clock domains, Riviera-PRO, SoC, SoC Verification, spec-tracer, system development, system verilog, systemverilog-based uvm, uvm-compliant environments, verification, verification ips, vips