Open side-bar Menu
 Aldec Design and Verification

Posts Tagged ‘high level synthesis’

FPGAs in an SoC World: How modern FPGA architecture influences verification methodologies

Thursday, June 1st, 2017

The SoC domination observed so far in the ASIC industry is coming to the FPGA world and changing the way FPGAs are used and FPGA projects are verified. The latest SoC FPGA devices  offer a very interesting alternative of reprogrammable logic powered with the microprocessor, usually ARM. With new types of devices there is always a need for extended verification methodology. SoC ASIC has so far been the main pioneer for advanced and highly scalable verification methodologies. Due to the complexity and size of such projects, ASIC labs were actually driving EDA vendors to deliver verification solutions for their projects.

 

With the growth of these projects, hardware emulation became a common tool which was then integrated with virtual platforms and labeled ‘hybrid co-emulation’. This hybrid solution offered a single verification platform for both software and hardware teams. Such platforms allow the performance of verification at the SoC level, allowing the entire project to be verified before the final design code is actually written and available for example, to perform the prototyping.

 

Hybrid emulation allows the connection of the work environment of software teams using virtual platforms with the hardware engineers using emulators. Why is this so important? The issue is, until now the software portion of the project worked on the virtual models, separate from the hardware portion. Connecting these two domains allows for testing of the project at the SoC level instead of the subsystems level, which in turn increases the coverage of testing and enables the detection of problems much earlier.

 

Hybrid_co-emulation_verification_system

Figure 1 – Hybrid co-emulation verification system.

(more…)

An Easier Path to Faster C with FPGAs

Monday, November 14th, 2016

For most scientists, what is inside a high-performance computing platform is a mystery. All they usually want to know is that a platform will run an advanced algorithm thrown at it. What happens when a subject matter expert creates a powerful model for an algorithm that in turn automatically generates C code that runs too slowly? FPGA experts have created an answer.

More and more, the general-purpose processor found in server-class platforms is yielding to something more optimized for the challenges of high-performance computing (HPC). Advanced algorithms like convolutional neural networks (CNNs), real-time analytics, and high-throughput sensor fusion are quickly overwhelming traditional hardware platforms. In some cases, HPC developers are turning to GPUs as co-processors and deploying parallel programming schemes – but at a massive cost in increased power consumption.

A more promising approach for workload optimization using considerably less power is hardware acceleration using FPGAs. Much as in the early days of FPGAs where they found homes in reconfigurable compute engines for signal processing tasks, technology is coming full circle and the premise is again gaining favor. The challenge with FPGA technology in the HPC community has always been how the scientist with little to no hardware background translates their favorite algorithm into a reconfigurable platform.
(more…)

Aldec and NEC reveal HLS shortcut at upcoming SoC Conference

Friday, October 18th, 2013

The University of California, Irvine (UCI) is popular for many things, but I recall during my school days that it was distinctly known among students for its underground tunnel network. The official story is that they were simply built to house heating and cooling pipes. Yet, the rumor persists that this complex maze of underground tunnels was constructed decades ago to provide safe passage for faculty members in case of student riots.

I’ll admit I would love to uncover these tunnels someday, unfortunately they have long been sealed off from curiosity seekers. I will, however, be at the UCI campus next week unraveling a different sort of maze for engineers attending the annual International SoC Conference. Aldec is once again a Platinum Sponsor for this popular academic conference, and this year I will be joined by NEC Corporation’s Dr. Wakabayashi to present a technical session:

(more…)

The WHAT is mandatory but the HOW is entirely optional

Monday, September 9th, 2013

You look confused. Perhaps I owe you an explanation. Anyone familiar with hardware design flow knows that it starts with specification and ends with implementation. The specification in this flow is the “What” – it defines what needs to be designed. The process for implementation is the “How” – it defines how you are going to achieve it.

Let’s break down just one part of the “How” or implementation – the Design Process. For many years hand-coded RTL has been used as the de facto method for implementation and it is still being used as predominant method for designing cutting-edge hardware. But does it follow that it is the most efficient method? I would say probably not, especially given the ever-growing complexity of the hardware.

For the rest of this article, visit the Aldec Design and Verification Blog.

Back from DAC

Tuesday, June 11th, 2013

Functional Verification Insights from Austin

Aldec Dac 2013

I just returned  back to the office from the 50th Design Automation Conference (DAC) which took place in Austin, TX, on June 2—6. As I began compiling my trip report, I thought that I might share some of my observations, especially for those who couldn’t attend this industry event but still wanted to gain some insight.

 

 

Conference itself

One of the reasons I like DAC is that it has always been the main industry event, attracting people from all over the world, and provides participants with the opportunity to meet most of their key customers, ecosystem partners, and competitors in a single location. From an exhibitor’s perspective, DAC is mainly about engaging with attendees on the floor, learning about their current and anticipated challenges, and educating them on how they can innovate and succeed using our product offerings.

(more…)

DownStream: Solutions for Post Processing PCB Designs
TrueCircuits: IoTPLL



Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
TechJobsCafe - Technical Jobs and Resumes EDACafe - Electronic Design Automation GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise