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Aldec Design and Verification

Posts Tagged ‘SoC Verification’

How Can Verification IPs Help the SoC Testing Process?

Monday, April 20th, 2015

How to use VIPs In Practice

Let’s assume that we are designing a new system on chip (SoC) which contains a processor and memory controller, as well as analog and digital peripherals like Ethernet, USB, 1-Wire and JTAG controllers.

Allow me to describe a typical verification process, and explain why I recommend the use of Verification IPs within the testing process.

Figure 1. Typical verification process

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Tags: Aldec, Emulation, HES-7, HES-DVM, ICE, In-circuit emulation, Kamil Rymarz, Monitor, Riviera-PRO, SoC Verification, Speed Adapter, Test, Transactor, Validation, Verification IP
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Back from DAC

Tuesday, June 11th, 2013

Functional Verification Insights from Austin

I just returned back to the office from the 50^th Design Automation Conference (DAC) which took place in Austin, TX, on June 2—6. As I began compiling my trip report, I thought that I might share some of my observations, especially for those who couldn’t attend this industry event but still wanted to gain some insight.

Conference itself

One of the reasons I like DAC is that it has always been the main industry event, attracting people from all over the world, and provides participants with the opportunity to meet most of their key customers, ecosystem partners, and competitors in a single location. From an exhibitor’s perspective, DAC is mainly about engaging with attendees on the floor, learning about their current and anticipated challenges, and educating them on how they can innovate and succeed using our product offerings.

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Tags: cdc, dac, design automation conference, driver software verification, ecosystem partners, fpga-based prototyping, Functional Verification, high level synthesis, hls, hw/sw co-verification, mixed-signal simulation, multimillion gate soc, multiple clock domains, Riviera-PRO, SoC, SoC and ASIC Prototyping, SoC Verification, spec-tracer, system development, system verilog, systemverilog-based uvm, uvm-compliant environments, verification, verification ips, vips
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